Multiplex delay line time compressor

Claim 1

A MULTIPLEX DELTIC COMPRISING: (A) A FIRST PULSE GENERATOR HAVING AN OUTPUT OF PULSES AT A FREQUENCY F; (B) A SECOND PULSE GENERATOR HAVING AN OUTPUT OF PULSES AT A FREQUENCY F/N WHERE N IS AN ODD OR EVEN INTEGER GREATER THAN UNITY; (C) A THIRD PULSE GENERATOR HAVING AN OUTPUT OF PULSES AT A FREQUENCY OF F/MN WHERE M IS AN ODD OR EVEN INTEGER GREATER THAN UNITY; (D) FIRST AND SECOND AND GATES EACH HAVING A SIGNAL INPUT, AN ENABLING INPUT AND AN OUTPUT; (D1) FIRST AND SECOND INHIBIT GATES EACH HAVING A SIGNAL INPUT, AN INHIBIT INPUT, AND AN OUTPUT; (E) A FIRST DEPAY MEANS HAVING AN INPUT AND AN OUTPUT, SAID FIRST DELAY MEANS INPUT CONNECTED TO SAID FIRST AND GATE OUTPUT AND SAID FIRST INHIBIT GATE OUTPUT, SAID FIRST DELAY MEANS OUTPUT CONNECTED TO SAID SECOND AND GATE SIGNAL INPUT SAID FIRST DELAY MEANS HAVING A TIME DELAY OF A PERIOD 1/F; (F) A PRECESSION PULSE GENERATOR HAVING FIRST, SECOND AND THIRD INPUTS CONNECTED TO THE OUTPUTS OF SAID FIRST, SECOND AND THIRD PULSE GENERATING MEANS, RESPECTIVELY, AND AN OUTPUT OF N PULSES AT A FREQUENCY OF F, SAID N PULSES OCCURRING ONCE IN EACH PERIOD OF 1/NM; (G) A SECOND DELAY MEANS HAVING A TOTAL DELAY OF N/F, AND HAVING AN INPUT AND AN OUTPUT, SAID SECOND DELAY MEANS OUTPUT CONNECTED TO SAID FIRST AND SECOND INHIBIT GATE SIGNAL INPUTS, SAID SECOND DELAY MEANS INPUT CONNECTED TO SAID SECOND AND GATE OUTPUT AND SAID SECOND INHIBIT GATE OUTPUT; (H) THE OUTPUT OF SAID THIRD PULSE GENERATING MEANS CONNECTED TO THE ENABLING INPUT OF SAID FIRST AND GATE AND THE INHIBIT INPUT OF SAID FIRST INHIBIT GATE; AND (I) THE OUTPUT OF SAID PRECESSION PULSE GENERATOR CONNECTED TO THE ENABLING INPUT OF SAID SECOND AND GATE AND THE INHIBIT INPUT OF SAID SECOND INHIBIT GATE; (J) THE SIGNAL INPUT OF SAID FIRST AND GATE BEING ADAPTED FOR CONNECTION TO A SIGNAL OF INTEREST; (K) WHEREBY ALL OF THE SIGNAL SAMPLES FROM SAID FIRST AND GATE WILL CIRCULATE N TIMES THROUGH SAID SECOND DELAY MEANS BETWEEN EACH NEW SIGNAL SAMPLE.