Reversible ring counter employing cascaded single scr stages

Claim 1

A REVERSIBLE COUNTER COMPRISING: A PLURALITY OF CASCADED STAGES, EACH STAGE INCLUDING AS A SWITCHING DEVICE, A SINGLE SILICON CONTROLLED RECTIFIER HAVING ANODE, CATHODE AND GATE ELECTRODES, ALL OF SAID CATHODES BEING CONNECTED TOGETHER TO A SOURCE OF REFERENCE POTENTIAL THROUGH A COMMON ELEMENT HAVING RESISTANCE; THE ANODE ELECTRODE OF THE SILICON CONTROL RECTIFIER OF EACH STAGE BEING CAPACITOR COUPLED TO THE GATE ELECTRODE OF THE SILICON CONTROL RECTIFIER OF THE PRECEDING AND SUCCEEDING STAGES; CIRCUIT MEANS FOR APPLYING A VOLTAGE TO SAID CASCADED STAGES, SAID VOLTAGE TURNING "ON" THE SILICON CONTROL RECTIFIER OF THE FIRST STAGE OF SAID CASCADED STAGES; EACH STAGE FURTHER INCLUDING A CAPACITOR CONNECTED IN PARALLEL WITH THE SILICON CONTROL RECTIFIER BETWEEN SAID CIRCUIT MEANS AND A REFERENCE POTENTIAL; CONTROL MEANS FOR APPLYING CONTROL PULSES TO SAID CASCADED STAGES, THE SUCCESSIVE APPLICATION OF SAID CONTROL PULSES SELECTIVELY RENDERING THE PULSED SILICON CONTROL RECTIFIER "ON" AND THE PRECEDING SILICON CONTROL RECTIFIER "OFF" IN A SEQUENTIAL MANNER.