Patent US3315232A successfully refreshed from Google Patents.
US3315232A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Resonant circuit timed translator matrix employing transistor gates
Assignee: AT&T Inc
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Filing: 1962-05-16
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Granted: 1967-04-18
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Expires: 1982-05-16
Abstract
No abstract record available.
Inventors
- 👤 Herbert S Feder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:50
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04J; H04J3/00; H04J3/20
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
152 words
IN A TRANSLATOR HAVING A PLURALITY OF CROSS-POINT CIRCUITS CONNECTED IN A MATRIX ARRAY DEFINED BY HORIZONTAL AND VERTICAL COORDINATE LEADS CONNECTED RESPECTIVELY TO A FIRST AND A SECOND PLURALITY OF DRIVE GATES, THE COMBINATION COMPRISING A CURRENT SOURCE CONNECTED TO SAID FIRST PLURALITY OF GATES, TIMING MEANS HAVING A PREDETERMINED TIMING CONTROL INTERVAL AND CONNECTED BETWEEN GROUND AND SAID SECOND PLURALITY OF GATES, SAID TIMING MEANS INCLUDING A RESONANT CIRCUIT HAVING AN INDUCTOR AND A CAPACITOR CONNECTED IN SERIES, MEANS FOR SELECTIVELY ACTIVATING ONE EACH OF SAID FIRST AND SECOND PLURALITY OF GATES AND SAID TIMING MEANS, A CURRENT CARRYING PATH FROM SAID SOURCE TO GROUND INCLUDING SAID SELECTED GATES AND CROSS-POINT CIRCUIT ASSOCIATED WITH SAID SELECTED GATES, AND MEANS IN SAID SELECTED GATES COOPERATING WITH SAID TIMING MEANS RESONANT CIRCUIT FOR ESTABLISHING A NONCONDUCTIVE CONDITION IN SAID GATES SIMULTANEOUSLY WITH THE TERMINATION OF SAID PREDETERMINED INTERVAL IN SAID TIMING MEANS.
Claim 2
Dependent Claim
152 words
IN A TRANSLATOR HAVING A PLURALITY OF CROSS-POINT CIRCUITS CONNECTED IN A MATRIX ARRAY DEFINED BY HORIZONTAL AND VERTICAL COORDINATE LEADS CONNECTED RESPECTIVELY TO A FIRST AND A SECOND PLURALITY OF DRIVE GATES, THE COMBINATION COMPRISING A CURRENT SOURCE CONNECTED TO SAID FIRST PLURALITY OF GATES, TIMING MEANS HAVING A PREDETERMINED TIMING CONTROL INTERVAL AND CONNECTED BETWEEN GROUND AND SAID SECOND PLURALITY OF GATES, SAID TIMING MEANS INCLUDING A RESONANT CIRCUIT HAVING AN INDUCTOR AND A CAPACITOR CONNECTED IN SERIES, MEANS FOR SELECTIVELY ACTIVATING ONE EACH OF SAID FIRST AND SECOND PLURALITY OF GATES AND SAID TIMING MEANS, A CURRENT CARRYING PATH FROM SAID SOURCE TO GROUND INCLUDING SAID SELECTED GATES AND CROSS-POINT CIRCUIT ASSOCIATED WITH SAID SELECTED GATES, AND MEANS IN SAID SELECTED GATES COOPERATING WITH SAID TIMING MEANS RESONANT CIRCUIT FOR ESTABLISHING A NONCONDUCTIVE CONDITION IN SAID GATES SIMULTANEOUSLY WITH THE TERMINATION OF SAID PREDETERMINED INTERVAL IN SAID TIMING MEANS.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1970-04-17 | 1970-10-17 | 1971-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1974-04-17 | 1974-10-17 | 1975-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1978-04-17 | 1978-10-17 | 1979-04-18 | $7700.00 | Window Closed / Lapsed |