Interconnection arrangement for integrated circuits

Claim 1

AN INTERCONNECTION ARRANGEMENT FOR INTERCONNECTING ACTIVE CIRCUIT ELEMENTS FORMED ON A WAFER COMPRISING A FIRST PLURALITY OF SPACED-PARALLEL CONDUCTORS IN A FIRST PLANE AND A SECOND PLURALITY OF SPACED-PARALLEL CONDUCTORS IN A SECOND PLANE AND SUPPORTED IN INSULATED FASHION ON SAID WAFER FOR INTERCONNECTING SAID ACTIVE ELEMENTS, SAID FIRST AND SAID SECOND CONDUCTORS BEING ARRANGED IN SUBSTANTIALLY TRANSVERSE FASHION AND LOCATED BETWEEN SAID ACTIVE ELEMENTS, SELECTED ONES OF SAID FIRST CONDUCTORS BEING CONNECTED TO SAID ACTIVE ELEMENTS, AND INSULATING MEANS POSITIONED BETWEEN SAID FIRST AND SAID SECOND CONDUCTORS AND PROVIDING ACCESS TO CORRESPONDING PORTIONS OF SAID FIRST CONDUCTORS, ADJACENT ONES OF SAID SECOND CONDUCTORS EACH HAVING AT LEAST ONE SUBSTANTIALLY ORTHOGONAL EXTENSION OPPOSITELY-DIRECTED WITH RESPECT TO SAID ORTHOGONAL EXTENSION OF THE OTHER FOR EFFECTING ELECTRICAL CONTACT TO SELECTED ONES OF SAID FIRST CONDUCTORS THROUGH SAID INSULATING MEANS.