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US3309531A Expired / Lapsed US ⏱️ 0.0 years remaining

Transistorized exclusive or logic circuit

Assignee: GTE Sylvania Inc
•
Filing: 1964-03-04
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Granted: 1967-03-14
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Expires: 1984-03-04
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Abstract

No abstract record available.

Inventors

  • 👤 Glenn R Hearn
  • 👤 Edward C Nellum

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 01:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/21; H03K19/212

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 257 words
A LOGIC CIRCUIT COMPRISING: FIRST AND SECOND TRANSISTORS EACH HAVING BASE, EMITTER AND COLLECTOR ELECTRODES; FIRST AND SECOND INPUT TERMINALS TO WHICH RESPECTIVE SOURCES OF INPUT VOLTAGE LEVELS ARE ADAPTED TO BE APPLIED; FIRST AND SECOND DIODES; A FIRST RESISTOR; SAID FIRST DIODE BEING CONNECTED BETWEEN SAID FIRST INPUT TERMINAL AND SAID FIRST RESISTOR; SAID SECOND DIODE BEING CONNECTED BETWEEN SAID SECOND INPUT TERMINAL AND SAID FIRST RESISTOR; A SECOND RESISTOR; MEANS CONNECTING SAID FIRST AND SECOND RESISTORS IN SERIES TO THE BASE ELECTRODE OF SAID FIRST TRANSISTOR; THIRD AND FOURTH DIODES; SAID THIRD AND FOURTH DIODES BEING RESPECTIVELY CONNECTED BETWEEN SAID FIRST AND SECOND INPUT TERMINALS AND ONE TERMINAL OF A THIRD RESISTOR, MEANS CONNECTING THE OTHER TERMINAL OF SAID THIRD RESISTOR TO THE BASE ELECTRODE OF SAID SECOND TRANSISTOR; A FIRST SOURCE OF POTENTIAL CONNECTED TO THE JUNCTION OF SAID THIRD AND FOURTH DIODES AND SAID THIRD RESISTOR; A SECOND SOURCE OF POTENTIAL OPPOSITE IN POLARITY TO SAID FIRST SOURCE OF POTENTIAL CONNECTED TO THE BASE OF SAID SECOND TRANSISTOR; FURTHER MEANS CONNECTING THE BASE ELECTRODE OF SAID FIRST TRANSISTOR TO SAID SECOND SOURCE OF POTENTIAL; A POINT OF REFERENCE POTENTIAL; MEANS DIRECTLY CONNECTING THE EMITTER ELECTRODES OF SAID FIRST AND SECOND TRANSISTORS TO SAID POINT OF REFERENCE POTENTIAL; MEANS DIRECTLY CONNECTING THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR TO THE JUNCTION BETWEEN SAID FIRST AND SECOND RESISTORS; A THIRD SOURCE OF POTENTIAL CONNECTED TO THE COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR; AND AN OUTPUT TERMINAL CONNECTED TO THE COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR.
Claim 2
Dependent Claim 257 words
A LOGIC CIRCUIT COMPRISING: FIRST AND SECOND TRANSISTORS EACH HAVING BASE, EMITTER AND COLLECTOR ELECTRODES; FIRST AND SECOND INPUT TERMINALS TO WHICH RESPECTIVE SOURCES OF INPUT VOLTAGE LEVELS ARE ADAPTED TO BE APPLIED; FIRST AND SECOND DIODES; A FIRST RESISTOR; SAID FIRST DIODE BEING CONNECTED BETWEEN SAID FIRST INPUT TERMINAL AND SAID FIRST RESISTOR; SAID SECOND DIODE BEING CONNECTED BETWEEN SAID SECOND INPUT TERMINAL AND SAID FIRST RESISTOR; A SECOND RESISTOR; MEANS CONNECTING SAID FIRST AND SECOND RESISTORS IN SERIES TO THE BASE ELECTRODE OF SAID FIRST TRANSISTOR; THIRD AND FOURTH DIODES; SAID THIRD AND FOURTH DIODES BEING RESPECTIVELY CONNECTED BETWEEN SAID FIRST AND SECOND INPUT TERMINALS AND ONE TERMINAL OF A THIRD RESISTOR, MEANS CONNECTING THE OTHER TERMINAL OF SAID THIRD RESISTOR TO THE BASE ELECTRODE OF SAID SECOND TRANSISTOR; A FIRST SOURCE OF POTENTIAL CONNECTED TO THE JUNCTION OF SAID THIRD AND FOURTH DIODES AND SAID THIRD RESISTOR; A SECOND SOURCE OF POTENTIAL OPPOSITE IN POLARITY TO SAID FIRST SOURCE OF POTENTIAL CONNECTED TO THE BASE OF SAID SECOND TRANSISTOR; FURTHER MEANS CONNECTING THE BASE ELECTRODE OF SAID FIRST TRANSISTOR TO SAID SECOND SOURCE OF POTENTIAL; A POINT OF REFERENCE POTENTIAL; MEANS DIRECTLY CONNECTING THE EMITTER ELECTRODES OF SAID FIRST AND SECOND TRANSISTORS TO SAID POINT OF REFERENCE POTENTIAL; MEANS DIRECTLY CONNECTING THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR TO THE JUNCTION BETWEEN SAID FIRST AND SECOND RESISTORS; A THIRD SOURCE OF POTENTIAL CONNECTED TO THE COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR; AND AN OUTPUT TERMINAL CONNECTED TO THE COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR.

References Cited (Backward Citations)

US2982868A Cited
US3023965A Cited
US3229117A Cited
US3196261A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1970-03-13 1970-09-12 1971-03-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1974-03-13 1974-09-12 1975-03-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1978-03-13 1978-09-12 1979-03-14 $7700.00 Window Closed / Lapsed

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