Patent US3307082A successfully refreshed from Google Patents.
US3307082A
Expired / Lapsed
US
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Switching arrangement
Assignee: CARL MURTH MASCHINEN- und ZAHNRADFABRIK
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Filing: 1964-12-01
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Granted: 1967-02-28
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Expires: 1984-12-01
Abstract
No abstract record available.
Inventors
- 👤 Reidmayr Georg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:29
CPC Classifications
B; B23; B23Q; B23Q15/00; H; H03; H03K; H03K17/00; H03K17/14; H03K17/51; H03K17/56; H03K17/60; H03K17/64
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
399 words
A SWITCHING ARRANGEMENT COMPRISING, IN COMBINATION, ELECTROMAGNETICALLY OPERABLE SWITCH MEANS INCLUDING AN ENERGIZABLE COIL AND CONTACT MEANS CHANGEABLE BETWEEN PREDETERMINED CIRCUIT-CLOSING AND CIRCUIT-OPENING POSITIONS DEPENDING UPON A CHANGE OF ENERGIZATION OF SAID COIL; FIRST ELECTRONIC CONTROL MEANS INCLUDING A FIRST TRANSISTOR HAVING EMITTER, COLLECTOR AND BASE ELECTRODES AND AN EMITTER-BASE PATH AND AN EMITTER-COLLECTOR PATH, SAID COLLECTOR ELECTRODE BEING CONNECTED TO ONE END OF SAID COIL OF SAID ELECTROMAGNETICALLY OPERABLE SWITCH MEANS FOR ENERGIZING SAID COIL WHEN A PREDETERMINED CONTROL POTENTIAL IS APPLIED TO SAID BASE ELECTRODE; SECOND ELECTRONIC CONTROL MEANS INCLUDING A SECOND TRANSISTOR HAVING EMITTER, COLLECTOR AND A BASE ELECTRODE, AN EMITTER-BASE PATH AND AN EMITTER-COLLECTOR PATH, THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR BEING CONNECTED TO THE BASE ELECTRODE OF SAID FIRST TRANSISTOR FOR CAUSING SAID FIRST TRANSISTOR TO DISCONTINUE ENERGIZING SAID COIL AS LONG AS SAID PREDETERMINED POTENTIAL IS APPLIED TO THE BASE ELECTRODES OF BOTH OF SAID FIRST AND SECOND TRANSISTORS; AND CIRCUIT MEANS FOR ENERGIZING SAID COIL, FOR APPLYING SAID CONTROL POTENTIAL TO SAID ELECTRONIC CONTROL MEANS, AND CONNECTING SAID FIRST AND SECOND ELECTRONIC CONTROL MEANS WITH EACH OTHER AND WITH SAID COIL IN A MANNER WHEREBY THE EMITTER-BASE PATH OF SAID FIRST TRANSISTOR AND THE EMITTERCOLLECTOR PATH OF SAID SECOND TRANSISTOR ARE CONNECTED IN PARALLEL, SAID CIRCUIT MEANS INCLUDING MEANS FOR APPLYING A DIRECT CURRENT POTENTIAL OF PREDETERMINED POLARITY TO THE OTHER END OF SAID COIL, A ZERO POTENTIAL TERMINAL HAVING ZERO POTENTIAL, FIRST CONTROL POTENTIAL MEANS FOR APPLYING A FIRST CONTROL POTENTIAL TO THE BASE ELECTRODE OF SAID FIRST TRANSISTOR TO CAUSE SAID FIRST TRANSISTOR TO BECOME CONDUCTIVE, SECOND CONTROL POTENTIAL MEANS FOR APPLYING A SECOND CONTROL POTENTIAL TO THE BASE ELECTRODE OF SAID SECOND TRANSISTOR TO CAUSE SAID SECOND TRANSISTOR TO BECOME CONDUCTIVE AND THEREBY TO CAUSE THE APPLICATION OF SAID FIRST CONTROL POTENTIAL TO THE BASE ELECTRODE OF SAID FIRST TRANSISTOR TO BECOME INEFFECTIVE THEREBY CAUSING SAID FIRST TRANSISTOR TO BECOME NON-CONDUCTIVE, A FIRST BIASING RESISTOR CONNECTED BETWEEN THE BASE ELECTRODE OF SAID FIRST TRANSISTOR AND A BIASING VOLTAGE SUPPLY FOR APPLYING TO SAID FIRST TRANSISTOR A BIASING POTENTIAL HAVING A POLARITY OPPOSITE TO THAT OF SAID DIRECT CURRENT POTENTIAL, AND A SECOND BIASING RESISTOR CONNECTED BETWEEN THE BASE ELECTRODE OF SAID SECOND TRANSISTOR AND A BIASING VOLTAGE SUPPLY FOR APPLYING TO SAID SECOND TRANSISTOR A BIASING POTENTIAL HAVING A POLARITY OPPOSITE TO THAT OF SAID DIRECT CURRENT POTENTIAL.
Claim 2
Dependent Claim
399 words
A SWITCHING ARRANGEMENT COMPRISING, IN COMBINATION, ELECTROMAGNETICALLY OPERABLE SWITCH MEANS INCLUDING AN ENERGIZABLE COIL AND CONTACT MEANS CHANGEABLE BETWEEN PREDETERMINED CIRCUIT-CLOSING AND CIRCUIT-OPENING POSITIONS DEPENDING UPON A CHANGE OF ENERGIZATION OF SAID COIL; FIRST ELECTRONIC CONTROL MEANS INCLUDING A FIRST TRANSISTOR HAVING EMITTER, COLLECTOR AND BASE ELECTRODES AND AN EMITTER-BASE PATH AND AN EMITTER-COLLECTOR PATH, SAID COLLECTOR ELECTRODE BEING CONNECTED TO ONE END OF SAID COIL OF SAID ELECTROMAGNETICALLY OPERABLE SWITCH MEANS FOR ENERGIZING SAID COIL WHEN A PREDETERMINED CONTROL POTENTIAL IS APPLIED TO SAID BASE ELECTRODE; SECOND ELECTRONIC CONTROL MEANS INCLUDING A SECOND TRANSISTOR HAVING EMITTER, COLLECTOR AND A BASE ELECTRODE, AN EMITTER-BASE PATH AND AN EMITTER-COLLECTOR PATH, THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR BEING CONNECTED TO THE BASE ELECTRODE OF SAID FIRST TRANSISTOR FOR CAUSING SAID FIRST TRANSISTOR TO DISCONTINUE ENERGIZING SAID COIL AS LONG AS SAID PREDETERMINED POTENTIAL IS APPLIED TO THE BASE ELECTRODES OF BOTH OF SAID FIRST AND SECOND TRANSISTORS; AND CIRCUIT MEANS FOR ENERGIZING SAID COIL, FOR APPLYING SAID CONTROL POTENTIAL TO SAID ELECTRONIC CONTROL MEANS, AND CONNECTING SAID FIRST AND SECOND ELECTRONIC CONTROL MEANS WITH EACH OTHER AND WITH SAID COIL IN A MANNER WHEREBY THE EMITTER-BASE PATH OF SAID FIRST TRANSISTOR AND THE EMITTERCOLLECTOR PATH OF SAID SECOND TRANSISTOR ARE CONNECTED IN PARALLEL, SAID CIRCUIT MEANS INCLUDING MEANS FOR APPLYING A DIRECT CURRENT POTENTIAL OF PREDETERMINED POLARITY TO THE OTHER END OF SAID COIL, A ZERO POTENTIAL TERMINAL HAVING ZERO POTENTIAL, FIRST CONTROL POTENTIAL MEANS FOR APPLYING A FIRST CONTROL POTENTIAL TO THE BASE ELECTRODE OF SAID FIRST TRANSISTOR TO CAUSE SAID FIRST TRANSISTOR TO BECOME CONDUCTIVE, SECOND CONTROL POTENTIAL MEANS FOR APPLYING A SECOND CONTROL POTENTIAL TO THE BASE ELECTRODE OF SAID SECOND TRANSISTOR TO CAUSE SAID SECOND TRANSISTOR TO BECOME CONDUCTIVE AND THEREBY TO CAUSE THE APPLICATION OF SAID FIRST CONTROL POTENTIAL TO THE BASE ELECTRODE OF SAID FIRST TRANSISTOR TO BECOME INEFFECTIVE THEREBY CAUSING SAID FIRST TRANSISTOR TO BECOME NON-CONDUCTIVE, A FIRST BIASING RESISTOR CONNECTED BETWEEN THE BASE ELECTRODE OF SAID FIRST TRANSISTOR AND A BIASING VOLTAGE SUPPLY FOR APPLYING TO SAID FIRST TRANSISTOR A BIASING POTENTIAL HAVING A POLARITY OPPOSITE TO THAT OF SAID DIRECT CURRENT POTENTIAL, AND A SECOND BIASING RESISTOR CONNECTED BETWEEN THE BASE ELECTRODE OF SAID SECOND TRANSISTOR AND A BIASING VOLTAGE SUPPLY FOR APPLYING TO SAID SECOND TRANSISTOR A BIASING POTENTIAL HAVING A POLARITY OPPOSITE TO THAT OF SAID DIRECT CURRENT POTENTIAL.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1970-02-27 | 1970-08-29 | 1971-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1974-02-27 | 1974-08-29 | 1975-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1978-02-27 | 1978-08-29 | 1979-02-28 | $7700.00 | Window Closed / Lapsed |