Single bit reversible shift register responsive to sequenced (transfer and clear) pair of input pulses

Claim 1

A SINGLE BIT REVERSIBLE SHIFT REGISTER HAVING A PLURALITY OF REGISTER ELEMENTS EACH COMPRISING TRANSISTOR FLIP-FLOP PAIRS OF EACH WHICH CONSIST OF TWO CROSS COUPLED TRANSISTORS BIASED FOR CONVENTIONAL FLIP-FLOP OPERATION WITH THE CORRESPONDING TRANSISTOR OF EACH PAIR WHEN CONDUCTING BEING INDICATIVE OF STORAGE OF THE INFORMATION BIT IN THAT ELEMENT, MEANS IN CIRCUIT WITH ONE TRANSISTOR OF EACH PAIR WHICH WHEN SUBJECTED TO A SEQUENCED PAIR OF INPUT PULSES SHIFTS THE INFORMATION BIT BETWEEN ELEMENTS IN ONE DIRECTION, MEANS IN CIRCUIT WITH SAID ONE TRANSISTOR OF EACH PAIR WHICH WHEN SUBJECTED TO A SEQUENCED PAIR OF INPUT PULSES SHIFTS THE INFORMATION BIT BETWEEN ELEMENTS IN THE OPPOSITE DIRECTION, MEANS PROVIDING AN OUTPUT VOLTAGE WHENEVER THE INFORMATION BIT IS IN ONE OR THE OTHER ENDMOST REGISTER ELEMENT OR THE REGISTER ELEMENTS RESPECTIVELY IMMEDIATELY ADJACENT THERETO, AND MEANS INCLUDED IN AT LEAST ONE REGISTER ELEMENT INTERMEDIATE THE SETS OF AFOREMENTIONED ENDMOST AND ADJACENT REGISTER ELEMENTS WHEREIN NO OUTPUT VOLTAGE IS PROVIDED.