Method of making semiconductor integrated circuit elements

Claim 1

THE FABRICATION OF A SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A PLURALITY OF ELECTRICALLY ISOLATED WAFERS COMPRISING THE STEPS OF: (A) PREPARING A SLICE OF MONOCRYSTALLINE SILICON, (B) TREATING THE SLICE TO FORM THEREIN A LAYER OF THE SAME CONDUCTIVITY TYPE BUT OF DIFFERING CONDUCTIVITY FROM THAT OF THE ORIGINAL SLICE, (C) PRODUCING ON ONE MAJOR SURFACE OF SAID SLICE AN ETCH RESISTANT MASK CONFORMING TO THE DESIRED ISOLATION PATTERN, (D) ETCHING SAID MASKED SURFACE TO PRODUCE A NETWORK OF SLOTS IN ACCORDANCE WITH THIS SAID PATTERN, (E) REMOVING THE ETCH-RESISTANT MASK, (F) DEPOSITING BY EVAPORATION IN THE NETWORK OF SLOTS AND ON SAID SLOTTED SURFACE A LAYER OF SILICON DIOXIDE, (G) REMOVING FROM THE OPPOSITE MAJOR SURFACE OF SAID SLICE A LAYER OF SEMICONDUCTOR MATERIAL OF A THICKNESS SO AS TO AT LEAST REACH THE BOTTOM OF SAID SLOTS THEREBY PRODUCING AN ARRAY OF ISOLATED SEMICONDUCTOR WAFERS IN SAID SLICE, (H) INTRODUCING SIGNIFICANT IMPURITIES INTO SAID WAFERS TO FORM THEREIN AREAS OF OPPOSITE CONDUCTIVITY TYPE DEFINING PN JUNCTIONS, (I) FORMING ON SAID OPPOSITE MAJOR SURFACE A DEPOSITED METAL FILM PATTERN INTERCONNECTING SAID CIRCUIT ELEMENTS.