Binary addition apparatus

Claim 1

IN AN ARITHMETIC SYSTEM: A MEMORY STORING A PLURALITY OF MULTIBIT WORDS; FIRST AND SECOND REGISTERS EACH CAPABLE OF STORING ONE OF SAID WORDS; MEANS FOR ACCESSING SELECTED WORDS FROM SAID MEMORY FOR STORAGE IN SAID FIRST AND SECOND REGISTERS; A PARALLEL ADDER CIRCUIT COMPRISED OF A PLURALITY OF ORDERED STAGES AT LEAST EQUAL IN NUMBER TO THE NUMBER OF BITS IN EACH OF SAID WORDS AND INCLUDING A FIRST STAGE HAVING A CARRY INPUT TERMINAL AND A LEAST STAGE HAVING A CARRY OUTPUT TERMINAL; MEANS FOR SIMULTANEOUSLY APPLYING WORDS STORED IN SAID FIRST AND SECOND REGISTERS TO SAID ADDER CIRCUIT; A CARRY FLIP-FLOP HAVING AN INPUT TERMINAL AND AN OUTPUT TERMINAL; MEANS COUPLING SAID LAST STAGE CARRY OUTPUT TERMINAL TO SAID CARRY FLIP-FLOP INPUT TERMINED FOR STORING THEREIN A CARRY INDICATION RESULTING FROM AN APPLICATION OF WORDS STORED IN SAID FIRST AND SECOND REGISTERS TO SAID ADDER CIRCUIT; AND MEANS COUPLING SAID CARRY FLIP-FLOP OUTPUT TERMINAL TO SAID FIRST STAGE CARRY INPUT TERMINAL FOR APPLYING THE CONTENT OF SAID CARRY FLIP-FLOP TO SAID ADDER CIRCUIT SIMULTANEOUSLY WITH A SUBSEQUENT APPLICATION OF WORDS STORED IN SAID FIRST AND SECOND REGISTERS TO SAID ADDER CIRCUIT.