Phase-locked loop with sideband rejecting properties

Claim 1

IN A SYSTEM WHEREIN A TRANSMITTER AND RECEIVER ARE ALTERNATELY KEYED ON AND OFF WITH A KEYING SIGNAL, SAID TRANSMITTER TRANSMITTING AN INTERRUPTED CARRIER WAVE AND SIDEBANDS IN RESPONSE TO SAID KEYING SIGNALS, SAID RECEIVER RECEIVING REFLECTION SIGNALS OF SAID INTERRUPTED CARRIER WAVE AND SIDEBANDS FROM A TARGET, SAID RECEIVER INCLUDING A PHASE-LOCKED LOOP HAVING A VOLTAGE CONTROLLED OSCILLATOR, THE IMPROVEMENT COMPRISING MEANS FOR DETECTING WHEN SAID PHASE-LOCKED LOOP HAS LOCKED IN PHASE WITH A SIDEBAND SIGNAL AND PRODUCING A "SIDEBAND LOCK" SIGNAL INDICATIVE THEREOF, MEANS RESPONSIVE TO SAID "SIDEBAND LOCK" SIGNAL FOR UNLOCKING SAID PHASE-LOCKED LOOP FROM THE PHASE OF SAID SIDEBAND SIGNAL, MEANS FOR DETECTING WHEN SAID PHASE-LOCKED LOOP HAS LOCKED TO THE PHASE OF ANY OF SAID RECEIVED SIGNALS AND PRODUCING AN "ANY LOCK" SIGNAL INDICATIVE THEREOF, AND MEANS RESPONSIVE TO THE PRESENCE OF SAID "ANY LOCK" SIGNAL AND THE ABSENCE OF SAID "SIDEBAND" LOCK" SIGNAL FOR INDICATING THAT SAID PHASE-LOCKED LOOP HAS LOCKED IN PHASE WITH SAID CARRIER.