High speed multiplier circuit

Claim 1

A CIRCUIT FOR MULTIPLYING A N-BIT MULTIPLICAND BY AN M-BIT MULTIPLIER COMPRISING: AN ARRAY OF ADDERS WITH R ADDERS PER MULTIPLICAND BIT, EACH OF SAID ADDERS HAVING A CARRY-DELAY TIME OF C, A SUM-DELAY TIME OF S AND A RECYCLE TIME FOR ITS LOGICAL ELEMENTS OF R, WHERE S AND R ARE INTEGRAL MULTIPLES OF C AND AT LEAST ONE OF THEM IS GREATER THAN C; MEANS FOR APPLYING EACH BIT OF THE MULTIPLICAND TO THE ADDERS FOR THAT BIT UNDER CONTROL OF THE BITS OF THE MULTIPLIER; MEANS FOR APPLYING THE CARRY OUTPUT FROM EACH ADDER TO THE NEXT ADDER TO BE UTILIZED FOR THE SAME MULTIPLICAND BIT; MEANS FOR APPLYING THE SUM OUTPUT FROM EACH ADDER TO THE ADDER S MULTIPLICAND BIT POSITIONS AND S ADDER POSITIONS ADVANCED FROM THE ADDER GENERATING THE SUM OUTPUT; WHEREBY S PARTIAL PRODUCTS ARE FORMED; AND AN ARRAY OF R(S-1) CONSOLIDATION ADDERS FOR CONSOLIDATING SAID S PARTIAL PRODUCTS INTO THE FINAL PRODUCT.