Differential amplifier and commutator system

Claim 1

IN A COMMUTATION SYSTEM, MEANS FOR MEASURING TRUE DIFFERENTIAL SIGNAL VOLTAGE IN THE PRESENCE OF COMMON MODE VOLTAGE AND AMPLIFIER BACK CURRENT COMPRISING, IN COMBINATION, A PLURALITY OF DIFFERENTIAL SIGNAL SOURCES, A PLURALITY OF SHIELDED TWO CONDUCTOR LINES EACH HAVING ONE OF SAID SIGNAL SOURCES CONNECTED ACROSS THE TERMINALS AT ONE END THEREOF, A PLURALITY OF CAPACITORS, EACH OF SAID CONDUCTOR LINES HAVING ONE OF SAID CAPACITORS CONNECTED ACROSS THE TERMINALS AT THE OTHER END OF THE LINE, EACH SAID CAPACITOR CONTINUOUSLY TRACKING AND HOLDING THE SIGNAL VOLTAGE PRODUCED BY THE SIGNAL SOURCE CONNECTED ACROSS ITS LINE THEREBY TO PROVIDE A VIRTUAL ZERO RESISTANCE SOURCE WHEREBY SPURIOUS SIGNAL VOLTAGE EFFECTS DUE TO IMPEDANCES IN THE LINE ARE SUBSTANTIALLY AVOIDED AND THE EFFECTIVE MAGNITUDE OF THE COMMON MODE VOLTAGES IS REDUCED BY AT LEAST AN ORDER OF MAGNITUDE, A DIFFERENTIAL AMPLIFIER HAVING TWO INPUTS AND AN OUTPUT, AND COMMUTATION MEANS OPERABLE TO CONNECT SAID TWO CONDUCTOR LINES IN SEQUENCE TO SAID AMPLIFIER INPUTS EACH RESPECTIVELY AT SAID TERMINALS AT SAID OTHER END THEREOF THEREBY TO CONNECT SAID CAPACITORS IN SEQUENCE ACROSS SAID AMPLIFIER INPUTS WHEREBY THE CAPACITOR HELD VOLTAGES ARE COMMUTATED INTO THE AMPLIFIER AND THE AMPLIFIED SIGNAL VOLTAGES APPEAR IN SEQUENCE ACROSS SAID AMPLIFIER OUTPUT, SAID COMMUTATION MEANS HAVING A SAMPLING PERIOD WHICH IS SHORT COMPARED TO THE TIME BETWEEN SAMPLES THEREBY SUBSTANTIALLY TO AVOID DEPELTION OF SAID CAPACITOR HELD VOLTAGES AT THE AMPLIFIER INPUTS WHILE THE SAME ARE BEING COMMUTATED INTO THE AMPLIFIER, EACH OF SAID CAPACITORS HAVING A VALUE WHICH LIES BETWEEN MINIMUM AND MAXIMUM VALUES AND PROVIDING A SIGNAL CHARGING RC TIME CONSTANT WHICH IS SHORT COMPARED TO SAID TIME BETWEEN SAMPLES AND A DISCHARGE RT TIME CONSTANT WITH RESPECT TO SAID INPUTS OF THE AMPLIFIER WHICH IS LONG COMPARED TO SAID SAMPLING PERIOD.