Patent US3260841A successfully refreshed from Google Patents.
US3260841A
Expired / Lapsed
US
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Tunnel diode majority logic serial binary adder/subtractor
Assignee: Westinghouse Electric Corp
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Filing: 1963-09-27
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Granted: 1966-07-12
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Expires: 1983-09-27
Abstract
No abstract record available.
Inventors
- 👤 Leland E Hayden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:56
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/504; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/10; G06F2207/00; G06F2207/38; G06F2207/48; G06F2207/4802; G06F2207/4818; G06F2207/4822; G06F2207/4828
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
337 words
A BINARY ADDER/SUBTRACTOR CIRCUIT OPERATIVE WITH INPUT SIGNALS COMPRISING, A FIRST ROW OF LOGIC ELEMENTS INCLUDING FOUR ONE-UNIT INPUT LOGIC ELEMENTS, EACH RECEIVING AS AN INPUT ONE OF SAID INPUT SIGNALS; A SECOND ROW OF LOGIC ELEMENTS INCLUDING TWO-UNIT INPUT LOGIC ELEMENTS AND ONE-UNIT INPUT LOGIC ELEMENTS, SAID TWO-UNIT LOGIC ELEMENTS OF SAID SECOND ROW RECEIVING AS INPUTS THE OUTPUTS OF SELECTED ONES OF SAID ONE-UNIT LOGIC ELEMENTS OF SAID FIRST ROW; A THIRD ROW OF LOGIC ELEMENTS INCLUDING ONE-UNIT INPUT LOGIC ELEMENTS AND AN INVERTER LOGIC ELEMENT, SAID ONE-UNIT LOGIC ELEMENTS OF SAID THIRD ROW RECEIVING AS INPUTS THE OUTPUTS OF SAID TWO-UNIT LOGIC ELEMENTS OF SAID SECOND ROW, SAID INVERTER LOGIC ELEMENT RECEIVING AS AN INPUT THE OUTPUT OF SAID ONE-UNIT LOGIC ELEMENT OF SAID SECOND ROW; A FOURTH ROW OF LOGIC ELEMENTS INCLUDING ONE-UNIT INPUT LOGIC ELEMENTS, A PLURALITY OF SAID ONE-UNIT LOGIC ELEMENTS OF SAID FOURTH ROW RECEIVING AS INPUTS THE OUTPUT OF ONE OF SAID ONE-UNIT LOGIC ELEMENTS OF SAID FOURTH ROW, SELECTED ONES OF SAID PLURALITY OF ONE-UNIT INPUT LOGIC ELEMENTS OF SAID FOURTH ROW PROVIDING AS OUTPUTS INPUTS TO SAID LOGIC ELEMENTS OF SAID SECOND ROW, ANOTHER OF SAID ONE-UNIT INPUT LOGIC ELEMENTS OF SAID FOURTH ROW RECEIVING AS AN INPUT THE OUTPUT OF SAID INVERTER LOGIC ELEMENT OF SAID THIRD ROW, ANOTHER OF SAID ONE-UNIT LOGIC ELEMENTS OF SAID FOURTH ROW RECEIVING AS AN INPUT THE OUTPUT OF ONE OF SAID ONE-UNIT INPUT LOGIC ELEMENTS OF SAID THIRD ROW; AN OUTPUT TWO-UNIT INPUT LOGIC ELEMENT RECEIVING AS INPUTS THE OUTPUTS OF SELECTED ONES OF SAID ONE-UNIT INPUT ELEMENTS OF SAID FOURTH ROW TO PROVIDE EITHER ONE OF A SUM AND DIFFERENCE SIGNAL OF SAID INPUT SIGNALS; AND A CLOCK PULSE SOURCE OPERATIVE TO PROVIDE SELECTIVELY RESET PULSES IN A TIMED PHASE RELATIONSHIP AS INPUTS TO THE LOGIC ELEMENTS WITH THE RESET PULSES BLOCKING INFORMATION FROM BEING TRANSMITTED THROUGH A LOGIC ELEMENT TO WHICH IT IS APPLIED WHILE THE ABSENCE OF A RESET PULSE PERMITS INFORMATION TO BE TRANSMITTED THERETHROUGH.
Claim 2
Dependent Claim
337 words
A BINARY ADDER/SUBTRACTOR CIRCUIT OPERATIVE WITH INPUT SIGNALS COMPRISING, A FIRST ROW OF LOGIC ELEMENTS INCLUDING FOUR ONE-UNIT INPUT LOGIC ELEMENTS, EACH RECEIVING AS AN INPUT ONE OF SAID INPUT SIGNALS; A SECOND ROW OF LOGIC ELEMENTS INCLUDING TWO-UNIT INPUT LOGIC ELEMENTS AND ONE-UNIT INPUT LOGIC ELEMENTS, SAID TWO-UNIT LOGIC ELEMENTS OF SAID SECOND ROW RECEIVING AS INPUTS THE OUTPUTS OF SELECTED ONES OF SAID ONE-UNIT LOGIC ELEMENTS OF SAID FIRST ROW; A THIRD ROW OF LOGIC ELEMENTS INCLUDING ONE-UNIT INPUT LOGIC ELEMENTS AND AN INVERTER LOGIC ELEMENT, SAID ONE-UNIT LOGIC ELEMENTS OF SAID THIRD ROW RECEIVING AS INPUTS THE OUTPUTS OF SAID TWO-UNIT LOGIC ELEMENTS OF SAID SECOND ROW, SAID INVERTER LOGIC ELEMENT RECEIVING AS AN INPUT THE OUTPUT OF SAID ONE-UNIT LOGIC ELEMENT OF SAID SECOND ROW; A FOURTH ROW OF LOGIC ELEMENTS INCLUDING ONE-UNIT INPUT LOGIC ELEMENTS, A PLURALITY OF SAID ONE-UNIT LOGIC ELEMENTS OF SAID FOURTH ROW RECEIVING AS INPUTS THE OUTPUT OF ONE OF SAID ONE-UNIT LOGIC ELEMENTS OF SAID FOURTH ROW, SELECTED ONES OF SAID PLURALITY OF ONE-UNIT INPUT LOGIC ELEMENTS OF SAID FOURTH ROW PROVIDING AS OUTPUTS INPUTS TO SAID LOGIC ELEMENTS OF SAID SECOND ROW, ANOTHER OF SAID ONE-UNIT INPUT LOGIC ELEMENTS OF SAID FOURTH ROW RECEIVING AS AN INPUT THE OUTPUT OF SAID INVERTER LOGIC ELEMENT OF SAID THIRD ROW, ANOTHER OF SAID ONE-UNIT LOGIC ELEMENTS OF SAID FOURTH ROW RECEIVING AS AN INPUT THE OUTPUT OF ONE OF SAID ONE-UNIT INPUT LOGIC ELEMENTS OF SAID THIRD ROW; AN OUTPUT TWO-UNIT INPUT LOGIC ELEMENT RECEIVING AS INPUTS THE OUTPUTS OF SELECTED ONES OF SAID ONE-UNIT INPUT ELEMENTS OF SAID FOURTH ROW TO PROVIDE EITHER ONE OF A SUM AND DIFFERENCE SIGNAL OF SAID INPUT SIGNALS; AND A CLOCK PULSE SOURCE OPERATIVE TO PROVIDE SELECTIVELY RESET PULSES IN A TIMED PHASE RELATIONSHIP AS INPUTS TO THE LOGIC ELEMENTS WITH THE RESET PULSES BLOCKING INFORMATION FROM BEING TRANSMITTED THROUGH A LOGIC ELEMENT TO WHICH IT IS APPLIED WHILE THE ABSENCE OF A RESET PULSE PERMITS INFORMATION TO BE TRANSMITTED THERETHROUGH.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1969-07-11 | 1970-01-10 | 1970-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1973-07-11 | 1974-01-10 | 1974-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1977-07-11 | 1978-01-10 | 1978-07-12 | $7700.00 | Window Closed / Lapsed |