Data transfer apparatus

Claim 1

APPARATUS FOR SYNCHRONOUSLY TRANSFERRING DATA BETWEEN A CENTRAL PROCESSOR UNIT OPERATING AT A FIRST FIXED SPEEDD AND A PERIPHERAL UNIT OPERATING AT A SECOND FIXED SPEED INDEPENDENT OF THE OPERATING SPEED OF SAID PROCESSOR UNIT, SAID APPARATUS COMPRISING A PLURALITY OF REGISTER STAGES EACH CAPABLE OF STORING ONE DECIMAL DIGIT, A PLURALITY OF CONTROL DEVICES EACH ASOCIATED WITH ONE OF SAID REGISTER STAGES TO INDICATE WHETHER THE CORRESPONDING STAGE IS CONDITIONED TO RECEIVE OR TRANSFER A DIGIT OF DATA, FIRST GATE CIRCUIT MEANS SYNCHRONIZED WITH THE OPERATION OF ONE OF SAID UNITS FOR SEQUENITALLY COUPLING THE INPUTS OF SAID REGISTER STAGES TO SAID ONE UNIT TO RECEIVE THE DATA THEREFROM, FIRST CONTROL CIRCUIT MEANS RESPONSIVE TO THE STATE OF SAID CONTROL DEVICES FOR ACTIVATING SAID GATE CIRCUIT MEANS ONLY WHEN THE NEXT REGISTER STAGE IN SEQUENCE IS CONDITINED TO RECEIVE A DIGIT OF SATA, SECOND GATE CIRCUIT MEANS SYNCHRONIZED WITH THE OPERATION OF THE OTHER ONE OF SAID UNITS FOR SEQUENTIALLY COUPLING THE OUTPUTS OF SAID REGISTER STAGES TO SAID OTHER UNIT TO TRANSFER THE STORED DATA TO SAID OTHER UNIT, AND SECOND CONTROL CIRCUIT MEANS RESPONSIVE TO THE STATE OF SAID CONTROL DEVICES FOR ACTIVATING SAID SECOND GATE CIRCUIT MEANS ONLY WHEN AT LEAST ONE OF SAID REGISTER STAGES IS CONDITIONED TO TRANSFER A DIGIT OF DATA TO SAID OTHER UNIT.