Patent US3249769A successfully refreshed from Google Patents.
US3249769A
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Standby power for a retentive memory logic circuitry
Assignee: Schneider Electric USA Inc
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Filing: 1964-05-18
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Granted: 1966-05-03
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Expires: 1984-05-18
Abstract
No abstract record available.
Inventors
- 👤 Robert C Mierendorf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:34
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/24; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0375
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
127 words
IN AN ELECTRICAL CONTROL SYSTEM, THE COMBINATION COMPRISING: A TRANSISTORIZED LOGIC MEMORY CIRCUIT HAVING A SELECTABLE BISTABLE SWITCHABLE STATE OF OPERATION, A NON MEMORY LOGIC CIRCUIT, A PRIMARY POWER SOURCE CONNECTED TO SUPPLY OPERATING D.C. POWER HAVING A PREDETERMINED POTENTIAL TO BOTH CIRCUITS, AND MEANS FOR MAINTAINING THE MEMORY CIRCUIT IN ITS LAST SWITCHED BISTABLE STATE IN EVENT THE PRIMARY SOURCE BECOMES INOPERATIVE, SAID MEANS INCLUDING: A STANDBY POWER SOURCE INCLUDING A RECHARGEABLE BATTERY HAVING AN OPERATING POTENTIAL LESS THAN THE PREDETERMINED POTENTIAL OF THE PRIMARY SOURCE, MEANS CONNECTING THE BATTERY IN PARALLEL WITH BOTH CIRCUITS AND THE PRIMARY SOURCE INCLUDING MEANS FOR PREVENTING THE BATTERY FROM SUPPLYING POWER TO THE PRIMARY SOURCE AND THE NON MEMORY LOGIC CIRCUIT DURING THE PERIOD THE PRIMARY SOURCE IS INOPERATIVE.
Claim 2
Dependent Claim
127 words
IN AN ELECTRICAL CONTROL SYSTEM, THE COMBINATION COMPRISING: A TRANSISTORIZED LOGIC MEMORY CIRCUIT HAVING A SELECTABLE BISTABLE SWITCHABLE STATE OF OPERATION, A NON MEMORY LOGIC CIRCUIT, A PRIMARY POWER SOURCE CONNECTED TO SUPPLY OPERATING D.C. POWER HAVING A PREDETERMINED POTENTIAL TO BOTH CIRCUITS, AND MEANS FOR MAINTAINING THE MEMORY CIRCUIT IN ITS LAST SWITCHED BISTABLE STATE IN EVENT THE PRIMARY SOURCE BECOMES INOPERATIVE, SAID MEANS INCLUDING: A STANDBY POWER SOURCE INCLUDING A RECHARGEABLE BATTERY HAVING AN OPERATING POTENTIAL LESS THAN THE PREDETERMINED POTENTIAL OF THE PRIMARY SOURCE, MEANS CONNECTING THE BATTERY IN PARALLEL WITH BOTH CIRCUITS AND THE PRIMARY SOURCE INCLUDING MEANS FOR PREVENTING THE BATTERY FROM SUPPLYING POWER TO THE PRIMARY SOURCE AND THE NON MEMORY LOGIC CIRCUIT DURING THE PERIOD THE PRIMARY SOURCE IS INOPERATIVE.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1969-05-02 | 1969-11-01 | 1970-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1973-05-02 | 1973-11-01 | 1974-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1977-05-02 | 1977-11-01 | 1978-05-03 | $7700.00 | Window Closed / Lapsed |