Inverter circuit utilizing silicon controlled rectifiers pulsed by phase delaying networks

Claim 1

AN INVERTER COMPRISING: (A) FIRST AND SECOND PAIRS OF ELECTRON DEVICES CONNECTED TO PASS A CURRENT IN ALTERNATE DIRECTIONS THROUGH LOAD, (B) FORWARD AND REVERSE PULSE NETWORKS CONNECTED TO SAID FIRST AND SECOND PAIRS OF ELECTRON DEVICES RESPECTIVELY, (C) EACH OF SAID PULSE NETWORKS BEING CONSTRUCTED TO CONVERT AN EXCITATION SIGNAL OF A GIVEN POLARITY INTO A TRIGGER VOLTAGE FOR TURNING ON THE ASSOCIATED PAIR OF ELECTRON DEVICES, EACH OF SAID PULSE NETWORKS BEING FURTHER CONNECTED TO THE RESPECTIVE PAIR SO AS TO BACK BIAS AN ELECTRON DEVICE IN THIS PAIR IN THE ABSENCE OF A TRIGGER VOLTAGE, (D) TRIGGER MEANS IN EACH OF SAID PULSE NETWORKS, (E) A SELECTIVE DELAY MEANS CONNECTED TO EACH TRIGGER MEANS, (F) A CAPACITOR IN EACH DELAY MEANS ARRANGED TO ACTUATE SAID TRIGGER MEANS WHEN THE CHARGE ON THE CAPACITOR REACHES A PREDETERMINED VALUE, (G) A RESISTOR CONNECTED IN SERIES WITH SAID CAPACITOR TO LIMIT THE CHANGING RATE OF THE CAPACITOR, (H) A DIODE SHUNTED ACROSS SAID RESISTOR TO PROVIDE A LOW RESISTANCE DISCHARGE PATH FOR SAID CAPACITOR, (I) REVERSING MEANS TO CAUSE SAID CAPACITOR TO CHARGE AND DISCHARGE IN ACCORDANCE WITH THE POLARITY OF THE EXCITATION SIGNAL, (J) AND PULSE INVERSION MEANS TO INVERT THE POLARITY OF THE EXCITATION SIGNAL SUPPLIED TO ONE PULSE NETWORK.