Circuit arrangement for producing potentials having equal absolute values but opposite sign depending on received signal combinations

Claim 1

A CIRCUIT ADAPTED TO RECEIVE FIRST AND SECOND SIGNALS FOR PRODUCING A GROUND POTENTIAL SIGNAL WHEN NO SIGNALS ARE RECEIVED, A SIGNAL HAVING A FIRST POTENTIAL OF GIVEN POLARITY AND AMPLITUDE WHEN ONLY SAID FIRST SIGNAL IS RECEIVED, AND A SIGNAL HAVING A SECOND POTENTIAL OF SAID GIVEN AMPLITUDE AND AN OPPOSITE POLARITY WHEN SAID FIRST AND SECOND SIGNALS ARE SUBSTANTIALLY SIMULTANEOUSLY RECEIVED, SAID CIRCUIT COMPRISING: A SOURCE OF VOLTAGE HAVING A FIRST VOLTAGE OUTPUT TERMINAL FOR TRANSMITTING SAID GROUND POTENTIAL, A SECOND VOLTAGE OUTPUT TERMINAL FOR TRANSMITTING SAID FIRST POTENTIAL, A THIRD VOLTAGE OUTPUT TERMINAL FOR TRANSMITTING SAID SECOND POTENTIAL, A FOURTH VOLTAGE OUTPUT TERMINAL FOR TRANSMITTING A POTENTIAL OF THE SAME POLARITY AND GREATER AMPLITUDE THAN SAID FIRST POTENTIAL, AND A FIFTH VOLTAGE OUTPUT TERMINAL FOR TRANSMITTING A POTENTIAL OF THE SAME POLARITY AND GREATER AMPLITUDE THAN SAID SECOND POTENTIAL; A FIRST BISTABLE CIRCUIT INCLUDING FIRST AND SECOND TRANSISTORS EACH HAVING EMITTER, COLLECTOR AND BASE ELECTRODES, MEANS FOR REGENERATIVELY INTERCONNECTING SAID FIRST AND SECOND TRANSISTORS, MEANS FOR CONNECTING ELECTRODES OF SAID FIRST TRANSISTOR TO VOLTAGE OUTPUT TERMINALS OF SAID SOURCE OF VOLTAGE FOR ENERGIZING SAID FIRST TRANSISTOR, RESISTOR MEANS FOR CONNECTING THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR TO SAID FIFTH VOLTAGE OUTPUT TERMINAL, MEANS FOR CONNECTING THE EMITTER ELECTRODE OF SAID SECOND TRANSISTOR TO SAID SECOND VOLTAGE OUTPUT TERMINAL; MEANS ADAPTED TO RECEIVE SAID FIRST SIGNAL FOR TRIGGERING SAID FIRST BISTABLE CIRCUIT TO A FIRST STABLE STATE WHEREIN AT LEAST SAID SECOND TRANSISTOR IS CONDUCTING; A SECOND BISTABLE CIRCUIT INCLUDING THIRD AND FOURTH TRANSISTORS EACH HAVING EMITTER, COLLECTOR AND BASE ELECTRODES, MEANS FOR REGENERATIVELY INTERCONNECTING SAID THIRD AND FOURTH TRANSISTORS, MEANS FOR CONNECTING ELECTRODES OF SAID FOURTH TRANSISTOR TO VOLTAGE OUTPUT TERMINALS OF SAID SOURCE OF VOLTAGE FOR ENERGIZING SAID FOURTH TRANSISTOR, RESISTOR MEANS FOR CONNECTING THE COLLECTOR ELECTRODE OF SAID THIRD TRANSISTOR TO SAID FOURTH VOLTAGE OUTPUT TERMINAL, MEANS FOR CONNECTING THE EMITTER ELECTRODE OF SAID THIRD TRANSISTOR TO SAID THIRD VOLTAGE OUTPUT TERMINAL; GATING MEANS INCLUDING A FIRST INPUT ADAPTED TO RECEIVE SAID SECOND SIGNAL AND A SECOND INPUT CONNECTED TO THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR FOR TRIGGERING SAID SECOND BISTABLE CIRCUIT TO A FIRST STABLE STATE WHEREIN AT LEAST SAID THIRD TRANSISTOR IS CONDUCTING WHEN SAID SECOND SIGNAL IS RECEIVED SUBSTANTIALLY SIMULTANEOUSLY WITH THE TRIGGERING OF SAID FIRST BISTABLE CIRCUIT TO SAID FIRST STABLE STATE; A FIRST UNILATERAL CONDUCTING DEVICE CONNECTING THE COLLECTOR ELECTRODES OF SAID SECOND AND THIRD TRANSISTORS; A SECOND UNILATERAL CONDUCTING DEVICE CONNECTING THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR TO SAID FIRST VOLTAGE OUTPUT TERMINAL FOR CLAMPING THE POTENTIAL OF THE EMITTER ELECTRODE OF SAID SECOND TRANSISTOR TO GROUND POTENTIAL; AND A SIGNAL OUTPUT TERMINAL CONNECTED TO THE COLLECTOR ELECTRODE OF SAID THIRD TRANSISTOR FOR TRANSMITTING THE GROUND POTENTIAL SIGNAL WHEN NEITHER OF SAID BISTABLE CIRCUITS IS IN A FIRST STABLE STATE, THE FIRST POTENTIAL SIGNAL WHEN ONLY SAID FIRST BISTABLE CIRCUIT IS IN A FIRST STABLE STATE, AND THE SECOND POTENTIAL SIGNAL WHEN BOTH OF SAID BISTABLE CIRCUITS ARE IN THE FIRST STABLE STATE.