Pulse generating circuit insensitive to input control switch contact bounce

Claim 1

IN COMBINATION, A SOURCE OF D.C. POTENTIAL, FIRST, SECOND AND THIRD TRANSISTOR HAVING THEIR EMITTER-COLLECTOR CIRCUITS CONNECTED ACROSS SAID SOURCE, MEANS IN CIRCUIT WITH SAID SOURCE AND THE BASES OF SAID FIRST AND THIRD TRANSISTORS RENDERING SUCH TRANSISTORS NORMALLY CONDUCTING, MEANS IN CIRCUIT WITH ONE SIDE OF THE EMITTERCOLLECTOR CIRCUIT OF SAID FIRST TRANSISTOR AND THE BASE OF SAID SECOND TRANSISTOR TO HOLD THE LATTER NON-CONDUCTING WHENEVER THE FORMER IS CONDUCTING, MEANS FOR SELECTIVELY CONNECTING THE BASE OF SAID FIRST TRANSISTOR TO ONE SIDE OF SAID SOURCE TO RENDER THE SAME NON-CONDUCTING AND SAID SECOND TRANSISTOR CONDUCTING, MEANS INCLUDING A CAPACITOR IN CIRCUIT WITH THE BASE OF SAID FIRST TRANSISTOR AND SAID SOURCE WHICH ACTS TO MAINTAIN SAID FIRST TRANSISTOR NONCONDUCTING FOR A CAPACITOR DISCHARGE INTERVAL FOLLOWING CONNECTION OF THE BASE OF SAID FIRST TRANSISTOR TO SAID ONE SIDE OF SAID SOURCE, MEANS INCLUDING A SECOND CAPACITOR IN CIRCUIT WITH ONE SIDE OF THE EMITTER-COLLECTOR CIRCUIT OF SAID SECOND TRANSISTOR AND THE BASE OF SAID THIRD TRANSISTOR WHICH ACTA UPON SAID SECOND TRANSISTOR BECOMING CONDUCTING TO RENDER SAID THIRD TRANSISTOR NON-CONDUCTING FOR AN INTERVAL DEPENDING UPON A DISCHARGE PERIOD OF SAID SECOND CAPACITOR, AND MEANS FOR DERIVING VOLTAGE PULSES ACROSS THE EMITTER COLLECTOR CIRCUIT OF SAID THIRD TRANSISTOR IN ACCORDANCE WITH THE LATTER''S INTERVAL OF NON-CONDUCTION.