Currency detectors

Claim 1

IN A CURRENCY DETECTOR, THE COMBINATION OF A MAGNETIC HEAD THAT ENGAGES A BILL T GENERATE VOLTAGE VARITIONS AND THAT HAS A LOW INDUCTANCE, A RESISTANCE-CAPACITANCE NETWORK THAT COUPLES SAID MAGNETIC HEAD TO A TRANSISTOR STAGE OF A PRE-AMPLIFIER, THE CAPACITOR OF SAID RESISTANCE-CAPACITANCE NETWORK BEING CONNECTED IN SERIES RELATION WITH THE COIL OF SAID MAGNETIC HEAD TO CONSTITUTE A SERIES RESONANT CIRCUIT, AND A SECOND RESISTANCE-CAPACITANCE NETWORK THAT COUPLES SAID TRANSISTOR STAGE TO A SECOND TRANSISTOR STAGE OF SAID PRE-AMPLIFIER, THE CAPACITOR OF THE FIRST SAID RESISTANCE-CAPACITANCE NETWORK HAVING A CAPACITANCE THAT COACTS WITH THE INDUCATANCE OF THE COIL OF SAID MAGNETIC HEAD TO MAKE SAID CAPACITOR AND THE COIL OF CONSTITUTE A SERIES RESONSTANT CIRCUIT THAT RESONATES AT A FREQUENCY BELOW BUT ADJACENT THE LOWER END OF A DESIRED FREQUENCY RANGE, SAID SERIES RESONANT CIRCUIT PROVIDING A HIGH GAIN FOR FREQUENCIES BELOW BUT ADJACENT SAID LOWER END OF SAID DESIRED FREQUENCY RANGE, SAID RESISTANCECAPACITANCE NETWORKS PASSING SIGNALS WITHIN SAID DESIRED FREQUENCY RANGE BUT SAID SERIES RESONANT CIRCUIT PROVIDING A HIGH RATE OF REJECTION BELOW THE RESONANT FREQUENCY THEREOF AND THUS BELOW SAID LOWER END OF SAID DESIRED FREQUENCY RANGE AND THEREBY MINIMIZING LOW FREQUENCY MODULATION OF VOLTAGE VARIATIONS GENERATED IN SAID COIL OF SAID MAGNETIC HEAD AS A BILL ENGAGES AND MOVES RELATIVE TO SAID MAGNETIC HEAD, THE FIRST SAID TRANSISTOR STAGE HAVING AN INPUT IMPEDANCE THAT IS VERY MUCH SMALLER THAN THE IMPEDANCE OF SAID SERIES RESONSANT CIRCUIT TO REDUCE THE Q OF THE COMBINATION OF SAID MAGNETIC HEAD AND PREAMPLIFIER, THEREBY PREVENTING SHARP PEAKING IN SAID DESIRED FREQUENCY RANGE, SAID SECOND TRANSISTOR STAGE HAVING A LOW INPUT IMPEDANCE THAT COACTS WITH SAID LOW INPUT IMPEDANCE OF THE FIRST SAID TRANSISTOR STAGE TO REDUCE THE EFFECT WHICH NOISE AND OTHER TRANSIENTS CAN HAVE UPON THE VOLTAGE VARIATIONS GENERATED IN SAID COIL OF SAID MAGNETIC HEAD, THE TRANSISTOR OF THE FIRST SAID TRANSISTOR STAGE AND THE TRANSISTOR OF SAID SECOND TRANSISTOR STAGE COACTING WITH THE DISTRIBUTED CAPACITIES OF SAID MAGNETIC HEAD TO PERMIT THE ATTAINMENT OF DESIRED FREQUENCIES ABOVE SAID LOWER END OF SAID DESIRED FREQUENCY RANGE AND TO LIMIT THE GAIN AT FREQUENCIES ADJACENT THE UPPER END SAID DESIRED FREQUENCY RANGE, SAID SERIES RESONANT CIRCUIT COACTING WITH SAID TRANSISTORS TO PROVIDE A SUBSTANTIALLY FLAT FREQUENCY RESPONSE THROUGOUT SAID DESIRED FREQUENCY RANGE, SAID TRANSISTORS COACTING WITH SAID DISTRIBUTED CAPACITIES AND WITH SAID LOW INPUT IMPEDANCES OF SAID TRANSISTOR STAGES TO INCREASE THE RATE OF REJECTION AT FREQUENCIES ABOVE SAID DESIRED FREQUENCY RANGE, SAID CAPACITOR OF THE FIRST SAID RESISTANCE-CAPACITANCE NETWORK COACTING WITH THE FIRST SAID TRANSISTOR STAGE TO CONSTITUTE A HIGH PASS AMPLIFIER, THE CAPACITOR OF SAID SECOND RESISTANCE-CAPACITANCE NETWORK COACTING WITH SAID SECOND TRANSISTOR STAGE TO CONSTITUTE A SECOND HIGH PASS AMPLIFIER.