Electronic bistable circuit

Claim 1

A BISTABLE CIRCUIT INCLUDING: FIRST, SECOND, THIRD, FOURTH, FIFTH AND SIXTH TRANSISTORS EACH HAVING A BASE, A COLLECTOR AND AN EMITTER ELECTRODE, THE EMITTER ELECTRODES OF SAID FIRST AND SECOND TRANSISTORS BEING CONNECTED IN COMMON TO THE COLLECTOR IN COMMON TO THE EMITTER ELECTRODES MEANS, CONNECTED IN COMMON TO THE EMITTER ELECTRODES OF SAID FIFTH AND SIXTH TRANSISTORS FOR SUUPPLYING THE SAME WITH A SUBSTANTIALLY CONSTANT CURRENT; THE BASE ELECTRODE OF SAID FIFTH TRANSISTOR BEING ADAPED FOR RECEIVING A PULSE INPUT SIGNAL, THE COLLECTOR ELECTRODE OF SAID FIFTH TRANSISTOR BEING CONNECTED IN COMMON TO THE EMITTER ELECTRODES OF SAID THIRD AND FOURTH TRANSISTORS; A FIRST IMPEDANCE CIRCUIT CONNECTING THE BASE ELECTRODE OF SAID FIRST TRANSISTOR TO THE BASE ELECTRODE OF SAID THIRD TRANSISTOR; A SECOND IMPEDANCE CIRCUIT CONNECTING THE BASE ELECTRODE OF SAID SECOND TRANSISTOR TO THE BASE ELECTRODE OF SAID FOURTH TRANSISTOR; A THIRD IMPEDANCE CIRCUUIT CONNECTING THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR TO THE BASE ELECTRODE OF SAID FIRST TRANSISTOR; AND A FOURTH IMPEDANCE CIRCUIT CONNECTING THE COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR TO THE BASE ELECTRODE OF SAID SECOND TRANSISTOR, SAID FIRST AND SECOND TRANSISTORS BEING THUS ARRANGED IN A COMMON EMITTER CIRCUIT CONFIGURATION AND HAVING THEIR BASES AND COLLECTORS CONDCTIVELY CROSSCONNECTED THROUG SAID THIRD AND FOURUTH IMPEDANCE CIRCUITS WHEREBY SAID FIRST AND SECOND TRANSISTORS FROM A TRIGGER PAIR HAVING TWO STABLE STATES OF OPERATING CONDITION, SAID THIRD AND FOURTH TRANSISTORS FORMING A GATING PAIR, SAID PULSE INPUT SIGNAL CONTROLLING THE TRANSFER OF THE FLOW OF SAID CONSTANT CURRENT TO SAID FIFTH AND SIXTH TRANSISTORS AND, THEREFORE, RESPECTIVELY TO SAID GATING PAIR AND SAID TRIGGER PAIR, SAID GATING PAIR THEN BEING ADAPTED FOR CONTROLLING THE BIASING POTENTIALS OF SAID TRIGGER PAIR SO AS TO PREPARE THE SWITCHING THEREOF FROM ONE STABLE STATE TO THE OTHER.