Synchronous delay amplifier employing plural blas and clock pulse sources

Claim 1

A SYNCHRONOUS DELAY AMPLIFIER FOR DELAYING A BINARY OUTPUT SIGNAL COMPRISING BISTABLE CIRCUIT MEANS HAVING FIRST AND SECOND INPUTS AND AN OUTPUT TERMINAL AND HAVING A HYSTERESIS CHARACTERISTIC, A FIRST CLOCK SIGNAL SORUCE, FIRST BIAS MEANS, FIRST DIODE MEANS COMPRISING A FIRST DIODE CONNECTED BETWEEN SAID SECOND INPUT OF SAID BISTABLE CIRCUIT MEANS AND FIRST BIAS MEANS, A SECOND DIODE CONNECTED BETWEEN SAID SECOND INPUT OF SAID BISTABLE CIRCUIT MEANS AND SAID FIRST CLOCK SIGNAL SOURCE, A SECOND CLOCK SIGNAL SOURCE, A SIGNAL INPUT TERMINAL, SECOND BIAS MEANS HAVING A POTENTIAL LEVEL SUBSTANTIALLY DIFFERENT FROM SAID FIRST BIAS MEANS, SECOND DIODE MEANS COMPRISING THIRD AND FOURTH DIODES CONNECTED IN SERIES BETWEEN THE SECOND BIAS POTENTIAL AND SAID SECOND CLOCK SIGNAL SOURCE, A FIFTH DIODE CONNECTED BETWEEN THE JUNCTION OF SAID THIRD AND FOURTH SERIES CONNECTED DIODES AND SAID SIGNAL INPUT TERMINAL, AND CIRCUIT MEANS FOR COUPLING A SIGNAL APPEARING AT SAID JUNCTION TO SAID BISTABLE CIRCUIT FIRST INPUT, SAID BISTABLE CIRCUIT BEING COMPRISED OF FIRST AND SECOND TRANSISTORS.