Race-preventing flip-flop switches by trailing edge of clock pulse applied through charged series capacitor

Claim 1

IN COMBINATION WITH A BISTABLE TRANSISTOR CIRCUIT HAVING A PAIR OF SYMMETRICAL INPUT CIRCUITS EACH OF WHICH COMPRISES A JUNCTION POINT AND MEANS FOR GATING A PLURALITY OF INPUT SIGNALS THERETO, MEANS FOR APPLYING A BIAS POTENTIAL TO SAID JUNCTION POINT WITH RESPECT TO A REFERENCE POINT, MEANS FOR RECEIVING SPACED PULSES OF FINITE DURATION, CAPACITIVE STORAGE MEANS HAVING FIRST AND SECOND TERMINALS, MEANS UNILATERALLY CONDUCTIVE IN MUTUALLY OPPOSITE DIRECTIONS FOR COUPLING SAID FIRST TERMINAL TO SAID JUNCTION POINT AND TO SAID PULSE RECEIVING MEANS RESPECTIVELY, AND MEANS UNILATERALLY CONDUCTIVE IN MUTUALLY OPPOSITE DIRECTIONS FOR COUPLING SAID SECOND TERMINAL TO SAID TRANSISTOR CIRCUIT AND TO SAID REFERENCE POINT RESPECTIVELY, SAID MEANS FOR COUPLING SAID FIRST AND SECOND TERMINALS TO SAID TRANSISTOR CIRCUIT AND TO SAID JUNCTION POINT RESPECTIVELY BEING OPPOSITELY POLED, SAID STORAGE MEANS BEING ADAPTED TO INITIATE CHARGING THEREOF UPON THE ARRIVAL OF THE LEADING EDGES OF SAID PULSES AND TO TRANSFER ITS CHARGE TO SAID TRANSISTOR CIRCUIT UPON THE ARRIVAL OF THE TRAILING PULSE EDGES.