Patent US3210529A successfully refreshed from Google Patents.
US3210529A
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Digital adder and comparator circuits employing ternary logic flements
Assignee: Unisys Corp
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Filing: 1962-08-29
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Granted: 1965-10-05
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Expires: 1982-08-29
Abstract
No abstract record available.
Inventors
- 👤 William H Hanson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 03:31
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/16; H03K19/162; G; G06; G06F; G06F7/00; G06F7/02; G06F7/026; G06F7/38; G06F7/48; G06F7/4824
Claims Analysis
Total Claims: 1
Claim 1
Independent Claim
36 words
A SIGNED TENARY FULL ADDER STAGE FOR GENERATING TERNARY VALUED SIGNALS C1 AND S1 REPRESENTATIVE OF THE SIGNED TENARY CARRY AND SUM RESPECTIVELY OF THE ITH DIGIT ORDER OF TWO SIGNED TERNARY NUMBERS OF THE FORM
References Cited (Backward Citations)
US3028088A
Cited
US2921737A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1968-10-04 | 1969-04-05 | 1969-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1972-10-04 | 1973-04-05 | 1973-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1976-10-04 | 1977-04-05 | 1977-10-05 | $7700.00 | Window Closed / Lapsed |