Circuit arrangement for operating a periodically activatable switching transistor

Claim 1

A CIRCUIT ARRANGEMENT FOR OPERATING A PERIODICALLY ACTIVATABLE SWITCHING TRANSISTOR CONTROLLING AN INDUCTIVE LOAD, PARTICULARLY THE DEFLECTOR COILS OF A CATHODE RAY TUBE, COMPRISING, IN COMBINATION, TRANSISTOR MEANS HAVING A BASE, A COLLECTOR AND AN EMITTER ELECTRODE; CONTROL MEANS FOR FURNISHING TO SAID TRANSISTOR MEANS A CONTROL IMPULSE COMPRISING A BLOCKING PERIOD WITH A BLOCKING VOLTAGE OF PREDETERMINED AMPLITUDE AND AN UNBLOCKING PERIOD WITH AN UNBLOCKING VOLTAGE OF PREDETERMINED AMPLITUDE; DAMPING DIODE MEANS CONNECTED IN PARALLEL WITH THE LOAD ACROSS THE AMPLITUDE AND AN UNBLOCKING VOLTAGE OF MEANS; AND TRANSFORMER MEANS COUPLING SAID CONTROL MEANS WITH SAID TRANSISTOR MEANS AND COMPRISING A SECONDARY WINDING IN CIRCUIT WITH SAID EMITTER AND BASE ELECTRODES OF SAID TRANSISTOR MEANS, THE PARAMETERS OF SAID CONTROL MEANS AND OF SAID TRANSISTOR MEANS BEING SO CHOSEN THAT SAID BLOCKING VOLTAGE AMPLITUDE OF SAID CONTROL IMPLUSE IS SUBSTANTIALLY EQUAL TO THE MAXIMUM PERMISSIBLE BLOCKING POTENTIAL OF SAID TRANSISTOR MEANS, AND THAT SAID UNBLOCKING VOLTAGE AMPLITUDE OF SAID CONTROL IMPLUSE IS A TIME FUNCTION OF THE VOLTAGE REQUIRED FOR SATURATING SAID TRANSISTOR MEANS, THE PRODUCT OF SAID BLOCKING PERIOD AND SAID MAXIMUM PERMISSIBLE BLOCKING VOLTAGE BEING SUBSTANTIALLY EQUAL TO THE INTEGRAL OF SAID TIME FUNCTION OF SAID UMBLOCKING VOLTAGE OVER THE DURATION OF SAID UNBLOCKING PERIOD.