Visual indicator for bistate units

Claim 1

AN INDICATOR ARRANGEMENT COMPRISING A FIRST TRANSISTOR, A FIRST POTENTIAL-DIVIDER NETWORK IN THE INPUT CIRCUIT OF SAID TRANSISTOR AND PROVIDING A FORWARD OR REVERSE BIAS THEREFOR IN DEPENDENCE UPON THE STATE OF A BISTATE SIGNAL APPLIED TO ITS INPUT CIRCUIT, A SECOND TRANSISTOR, A SECOND POTENTIAL-DIVIDER NETWORK INCLUDING RESISTANCE MEANS DIRECTLY CONNECTING THE COLLECTOR OF SAID FIRST TRANSISTOR TO THE BASE OF SAID SECOND TRANSISTOR, SAID SECOND POTENTIALDIVIDER NETWORK PROVIDING FOR SAID SECOND TRANSISTOR A BIAS OPPOSITE TO THE BIAS CONCURRENTLY PROVIDED BY SAID FIRST POTENTIAL-DIVIDER NETWORK FOR SAID FIRST TRANSISTOR, A LOW-VOLTAGE FILAMENT TYPE INDICATOR BULB IN THE OUTPUT CIRCUIT OF SAID SECOND TRANSISTOR AND ENERGIZED WHEN SAID SECOND POTENTIAL-DIVIDER NETWORK PROVIDES A FORWARD BIAS, AND A MEMORY CIRCUIT INCLUDING A DIODE CONNECTED BETWEEN THE OUTPUT CIRCUIT OF SAID SECOND TRANSISTOR AND THE INPUT CIRCUIT OF SAID FIRST TRANSISTOR FOR MAINTAINING SAID INDICATOR BULB IN ENERGIZED STATE AFTER DISCONTINUANCE OF THE INPUT SIGNAL STATE WHICH INITIALLY SHIFTED WITH CONSEQUENT SHIFT TRANSISTOR FROM FORWARD TO REVERSE WITH CONSEQUENT SHIFT OF SAID BIAS ON THE SECOND TRANSISTOR FROM REVERSE TO FORWARD.