Feedback conditioned coincident pulse responsive bistable circuits

Claim 1

IN A TRIGGER CIRCUIT, THE COMBINATION COMPRISING: A BISTABLE DEVICE ADAPTED TO PROVIDE A HIGH VOLTAGE STATE IN RESPONSE TO A FIRST INPUT AND A LOW VOLTAGE STATE IN RESPONSE TO A SECOND INPUT; AN INPUT CIRCUIT COUPLED TO SAID BISTABLE CIRCUIT AND ADAPTED TO ACCOMMODATE FIRST AND SECOND DATA SIGNAL LEVELS; A CLOCK CIRCUIT COUPLED TO SAID BISTABLE CIRCUIT AND ADAPTED TO PROVIDE TIMED SIGNALS; A CONTROL CIRCUIT COUPLED TO SAID CLOCK CIRCUIT AND INPUT CIRCUIT AND OPERATIVELY RESPONSIVE TO THE VOLTAGE STATE OF SAID BISTABLE DEVICE, SAID CONTROL CIRCUIT CONDITIONED BY A LOW VOLTAGE OUTPUT FROM SAID BISTABLE DEVICE TO BE OPERATIVE, UPON THE SIMULTANEOUS APPLICATION OF SAID FIRST DATA SIGNAL LEVEL AT SAID INPUT CIRCUIT AND A TIMED SIGNAL FROM SAID CLOCK CIRCUIT TO PRODUCE A FIRST OUTPUT TO CAUSE SAID BISTABLE DEVICE TO ASSUME ITS HIGH VOLTAGE STATE, SAID CONTROL CIRCUIT FURTHER OPERATIVE WHEN CONDITIONED BY SAID HIGH VOLTAGE STATE FROM SAID BISTABLE DEVICE, TO RESPOND TO A TIMED SIGNAL FROM SAID CLOCK CIRCUIT TO PRODUCE A SECOND OUTPUT WHEREBY SAID BISTABLE DEVICE ASSUMES ITS LOW VOLTAGE STATE.