Relaxation oscillator with timing capacitor charge path isolated from transistor leakage current

Claim 1

A TRANSISTOR RELAXATION OSCILLATOR COMPRISING A TRANSISTOR HAVING A CONTROL ELECTRODE, AN OUTPUT ELECTRODE, AND A COMMON ELECTRODE, A SOURCE OF OPERATING POTENTIAL HAVING FIRST AND SECOND TERMINALS, A SERIES CIRCUIT COMPRISING A CAPACITOR AND A RESISTOR CONNECTED IN THE ORDER BETWEEN SAID FIRST AND SECOND TERMINALS, MEANS CONNECTING SAID COMMON AND OUTPUT ELECTRODES TO SAID FIRST AND SECOND TERMINALS RESPECTIVELY, POSITIVE FEEDBACK CIRCUIT MEANS COUPLED BETWEEN SAID OUTPUT AND CONTROL ELECTRODES, CIRCUIT MEANS CONNECTED TO SAID CONTROL ELECTRODE FOR PROVIDING A SUBSTANTIALLY CONSTANT BIAS VOLTAGE TO SAID CONTROL ELECTRODE WHEREBY SAID TRANSISTOR IS BIASED FOR CONTINUOUS CONDUCTION WITH SUBSTANTIALLY MAXIMUM AMPLIFICATION, RECTIFIER MEANS, AND CIRCUIT MEANS CONNECTING SAID RECTIFIER MEANS BETWEEN SAID CONTROL ELECTRODE AND THE JUNCTION OF SAID RESISTOR AND CAPACITOR, AND RECTIFIER MEANS BEING POLED TO BE UNBLOCKED ONLY WHEN THE VOLTAGE AT SAID JUNCTION HAS A POLARITY WITH RESPECT TO SAID BIAS VOLTAGE THAT WOULD SUSTAIN THE CONDUCTION OF SAID TRANSISTOR AND BLOCK WHEN THE JUNCTION VOLTAGE HAS A POLARITY WITH RESPECT TO SAID BIAS VOLTAGE THAT WOULD REDUCE THE CONDUCTION OF THE TRANSISTOR.