Semiconductor bistable circuit with integral gate

Claim 1

A FLIPFLOP AND INTEGRAL GATE CIRCUIT COMPRISING: (1) A FIRST TRANSISTOR PROVIDED WITH BASE, COLLECTOR AND EMITTER ELECTRODES TO FORM ONE SIDE OF SAID FLIPFLOP; (2) RESPECTIVE SOURCES OF ENERGIZING POTENTIAL CONNECTED TO SAID ELECTRODES; (3) AN "OR" GATE HAVING FIRST AND SECOND INPUTS FOR RECEIVING BIAS CURRENT SIGNALS AND AN OUTPUT COUPLED TO SAID BASE TO SET THE STATE OOF SAID FLIPFLOP; (4) A FIRST DIFFERENCE AMPLIFIER FORMING THE OTHER SIDE OF SAID FLIPFLOP AND HAVING A GROUNDED INPUT, A SECOND INPUT COUPLED TO SAID EMITTER, AND AN OUTPUT CONNECTED TO SAID FIRST INPUT OF SAID "OR" CIRCUIT TO FURNISH BIAS CURRENT THERETO; (5) A SECOND TRANSISTOR PROVIDED WITH A BASE TO RECEIVE CONTROL SIGNALS TO SWITCH SAID SECOND TRANSISTOR OFF OR ON, A COLLECTOR CONNECTED TO SAID SECOND INPUT OF SAID "OR" GATE TO FURNISH BIAS CURRENT THERETO, AND AN EMITTER; (6) A SOURCE OF ENERGIZING POTENTIAL COUPLED TO SAID EMITTER; (7) A SECOND DIFFERENCE AMPLIFIER HAVING A FIRST GROUNDED INPUT, A SECOND INPUT AND FIRST AND SECOND OUTPUTS CONNECTED RESPECTIVELY TO SAID FIRST AND SECOND INPUTS OF SAID "OR" GATE, TO PROVIDE A BIAS CURRENT NORMALLY TO SAID FIRST INPUT OF SAID "OR" GATE; (8) A SOURCE OF GATING VOLTAGE CONNECTED TO SAID SECOND INPUT OF SAID SECOND DIFFERENCE AMPLIFIER TO SWITCH THE OUTPUT BIAS CURRENT FROM SAID SECOND DIFFERENCE AMPLIFIER TEMPORARILY TO SAID SECOND INPUT OF SAID "OR" GATE, THE MAGNITUDES OF SAID BIAS CURRENTS FROM THE OUTPUTS OF SAID DIFFERENCE AMPLIFIERS AND SAID SECOND TRANSISTOR BEING SUBSTANTIALLY EQUAL, THEREBY ALLOWING SAID SECOND TRANSISTOR TO CONTROL SAID "OR" GATE ONLY WHEN SAID SECOND DIFFERENCE AMPLIFIER FURNISHES BIAS CURRENT TO SAID SECOND "OR" GATE INPUT; AND (9) FIRST AND SECOND OUTPUT TERMINALS COUPLED TO RESPECTIVE SIDES OF SAID FLIPFLOP FOR INDICATING THE STATE THEREOF.