Delay flip-flop circuit

Claim 1

IN COMBINATION WITH A FLIP-FLOP CIRCUIT INCLUDING FIRST AND SECOND COMPLEMENTARY TYPE TRANSISTORS, EACH HAVING AN EMITTER, A COLLECTOR, AND BASE WHEREIN FIRST MEANS ARE PROVIDED COUPLING THE COLLECTOR OF SAID FIRST TRANSISTOR TO THE BASE OF SAID SECOND TRANSISTOR FOR RENDERING SAID SECOND TRANSISTOR NONCONDUCTIVE WHEN SAID FIRST TRANSISTOR IS NONCONDUCTIVE AND WHEREIN SECOND MEANS ARE PROVIDED COUPLING THE COLLECTOR OF SAID SECOND TRANSISTOR TO THE BASE OF SAID FIRST TRANSISTOR FOR RENDERING SAID FIRST TRANSISTOR CONDUCTIVE WHEN SAID SECOND TRANSISTOR IS CONDUCTIVE AND WHEREIN THIRD MEANS ARE PROVIDED RESPECTIVELY, COUPLING SAID FIRST AND SECOND TRANSISTOR EMITTERS TO SOURCES OF REFERENCE POTENTIAL, AN INPUT CIRCUIT FOR RESPECTIVELY CONTROLLING SAID FIRST AND SECOND TRANSISTORS, SAID INPUT CIRCUIT COMPRISING: INPUT SIGNAL SOURCE MEANS CAPABLE OF SELECTIVELY PROVIDING FIRST AND SECOND OUTPUT SIGNALS; CLOCK PULSE SOURCE MEANS FOR PERIOCICALLY PROVIDING CLOCK PULSES;