Computer

Claim 1

DECIMAL-TO-BINARY CONVERTER COMPRISING, IN COMBINATION: (A) DECIMAL-TO-BINARY ENCODING MEANS FOR ENCODING A BINARY NUMBER; (B) AN N-DECADE SHIFTING REGISTER CONNECTED TO SAID ENCODING MEANS FOR DIVIDING THE BINARY ENCODED DECIMAL NUMBER, EACH OF SAID SHIFTING REGISTER DECADES INCLUDING A SERIES OF STORAGE ELEMENTS AND A SERIES OF INTERMEDIATE STORAGE ELEMENTS, EACH OF SAID STORAGE AND INTERMEDIATE STORAGE ELEMENTS CONSTITUTING A STAGE CORRESPONDING RESPECTIVELY TO A BINARY DIGITAL POSITION OF A BINARY NUMBER, SAID STORAGE ELEMENTS BEING CONNECTED TO A FIRST COMMON INPUT AND SAID INTERMEDIATE SOTRAGE ELEMENTS BEING CONNECTED TO A SECOND COMMON INPUT, WHEREBY A PULSE APPEARING ON SAID FIRST COMMON INPUT SHIFTS BINARY DIGIT INFORMATION STORED IN SAID STORAGE ELEMENTS TO SAID INTERMEDIATE STORAGE ELEMENTS AND A PULSE APPEARING ON SAID SECOND COMMON INPUT SHIFTS SAID INFORMATION BACK TO SAID STORAGE ELEMENTS, SAID BINARY DIGITS BEING SHIFTED DOWNWARDLY BY ONE DIGIT POSITION UPON BEING SHIFTED FROM SAID INTERMEDIATE STORAGE ELEMENTS TO SAID STORAGE ELEMENTS; AND (C) ADDITION MATRIX MEANS HAVING (N-1) DECADES, EACH OF SAID ADDITION MATRIX DECADES BEING CONNECTED TO A RESPECTIVE ONE OF SAID SHIFTING REGISTER DECADES EXCEPT THE HIGHEST-ORDER SHIFTING REGISTER DECADE FOR CONTROLLING THE RESPECTIVE SHIFTING REGISTER DECADE AND TO BE CONTROLLED THEREBY, EACH OF SAID MATRIX DECADES HAVING A CONTROL INPUT CONNECTED TO THE LOWEST-ORDER STAGE OF THE SHIFTING REGISTER DECADE OF THE NEXT-HIGHEST ORDER, SAID CONNETIONS BETWEEN SAID MATRIX DECADES AND SAID SHIFTING REGISTER DECADES BEING THE SOLE CONNECTION TO AND FROM SAID MATRIX DECADES.