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Patent US3145342A successfully refreshed from Google Patents.
US3145342A
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Universal logical element
Assignee: COMPUTER CONTROL COMPANY Inc
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Filing: 1961-03-15
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Granted: 1964-08-18
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Expires: 1981-03-15
Abstract
No abstract record available.
Inventors
- 👤 Howard H Hill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:24
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K5/00; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
150 words
A UNIVERSAL LOGIC PACKAGE COMPRISING: AT LEAST ONE AND GATE ADAPTED TO PROVIDE EITHER OF TWO INPUT SIGNAL VOLTAGE LEVELS DEPENDING UPON THE CONDITION OF SAID GATE; A FLIP-FLOP; A PAIR OF TRANSISTORS OF THE SAME POLARITY TYPE HAVING THEIR EMITTERS CONNECTED TO ONE ANOTHER AND HAVING THEIR COLLECTORS RESPECTIVELY COUPLED TO SEPARATE INPUTS OF SAID FLIP-FLOP, THE BASE OF A FIRST OF SAID TRANSISTORS BEING CONNECTED TO THE OUTPUT OF SAID GATE; MEANS FOR FORWARDLY BIASING SAID COLLECTORS WITH A PREDETERMINED VOLTAGE; MEANS FOR IMPOSING A REFERENCE BIAS VOLTAGE ON THE BASE OF THE SECOND OF SAID TRANSISTORS; A PULSE CURRENT SOURCE CONNECTED TO SAID EMITTERS; AND DELAYING THE APPLICATION TO SAID BASE OF ONLY ONE OF SAID SIGNAL LEVELS IN THE EVENT SAID ONE OF SAID SIGNAL LEVELS ARISES DURING THE PERIOD OF A PULSE WHEN SAID PULSE IS BEING CONDUCTED BY SAID SECOND TRANSISTOR TO SAID FLIP-FLOP.
Claim 2
Dependent Claim
150 words
A UNIVERSAL LOGIC PACKAGE COMPRISING: AT LEAST ONE AND GATE ADAPTED TO PROVIDE EITHER OF TWO INPUT SIGNAL VOLTAGE LEVELS DEPENDING UPON THE CONDITION OF SAID GATE; A FLIP-FLOP; A PAIR OF TRANSISTORS OF THE SAME POLARITY TYPE HAVING THEIR EMITTERS CONNECTED TO ONE ANOTHER AND HAVING THEIR COLLECTORS RESPECTIVELY COUPLED TO SEPARATE INPUTS OF SAID FLIP-FLOP, THE BASE OF A FIRST OF SAID TRANSISTORS BEING CONNECTED TO THE OUTPUT OF SAID GATE; MEANS FOR FORWARDLY BIASING SAID COLLECTORS WITH A PREDETERMINED VOLTAGE; MEANS FOR IMPOSING A REFERENCE BIAS VOLTAGE ON THE BASE OF THE SECOND OF SAID TRANSISTORS; A PULSE CURRENT SOURCE CONNECTED TO SAID EMITTERS; AND DELAYING THE APPLICATION TO SAID BASE OF ONLY ONE OF SAID SIGNAL LEVELS IN THE EVENT SAID ONE OF SAID SIGNAL LEVELS ARISES DURING THE PERIOD OF A PULSE WHEN SAID PULSE IS BEING CONDUCTED BY SAID SECOND TRANSISTOR TO SAID FLIP-FLOP.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1967-08-18 | 1968-02-17 | 1968-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1971-08-18 | 1972-02-17 | 1972-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1975-08-18 | 1976-02-17 | 1976-08-18 | $7700.00 | Window Closed / Lapsed |