Pulse generating circuit having a high repetition rate utilizing avalanche transistor-coaxial line combination

Claim 1

A PLUSE GENERATING CIRCUIT COMPRISING, IN COMBINATION, A TRANSISTOR HAVING A BASE AND FIRST AND SECOND ELECTRODES, SAID TRANSISTOR BEING CAPABLE OF EXPERIENCING AN AVALANCHE BREAKDOWN WHEN PREDETERMINED BIAS CONDITIONS EXIST AT SAID BASE AND SAID FIRST AND SECOND ELECTRODES, A COAXIAL LINE, MEANS FOR COUPLING ONE SIDE OF SAID COAXIAL LINE TO SAID SECOND ELECTRODE, MEANS FOR CONNECTING THE OTHER SIDE OF SAID COAXIAL LINE TO A SOURCE OF CHARGING VOLTAGE, AN OUTPUT CIRCUIT CONNECTED BETWEEN ONE OF SAID ELECTRODES AND A REFERENCE POTENTIAL, MEANS FOR APPLYING A BLOCKING BIAS TO SAID BASE TO MAINTAIN SAID TRANSISTOR NEAR THE AVALANCHE BREAKDOWN POINT WHEN SAID COAXIAL LINE IS FULLY CHARGED, AND MEANS FOR PERIODICALLY COUPLING TRIGGER PULSES TO SAID BASE FOR OVERCOMING SAID BLOCKING BIAS AND DRIVING SAID TRANSISTOR INTO AN AVALANCHE BREAKDOWN, SAID COAXIAL LINE DISCHARGING THROUGH SAID TRANSISTOR DURING AVALANCHE, WHEREBY OUTPUT PULSES ARE GENERATED ACROSS SAID OUTPUT CIRCUIT, AND MEANS FOR COUPLING INVERTED OUTPUT PULSES BACK TO THE BASE OF SAID TRANSISTOR TO SHORTEN THE EFFECTIVE LENGTH OF EACH TRIGGER PULSE.