Patent US3136901A successfully refreshed from Google Patents.
US3136901A
Expired / Lapsed
US
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Information handling apparatus
Assignee: RCA Corp
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Filing: 1962-03-01
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Granted: 1964-06-09
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Expires: 1982-03-01
Abstract
No abstract record available.
Inventors
- 👤 Richard H Yen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:41
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
144 words
A LOGIC CIRCUIT FOR INDICATING THE PARITY OF A SET OF BINARY BITS COMPRISING: MEANS SUPPLYING INPUT SIGNALS REPRESENTING SAID BITS AND THE COMPLEMENTS OF SAID BITS, A SIGNAL REPRESENTING A BINARY "1" HAVING A FIRST VALUE AND A SIGNAL REPRESENTING A BINARY "O" HAVING A SECOND, DIFFERENT VALUE; A FIRST SET OF COINCIDENCE GATES EACH HAVING AT LEAST THREE INPUT TERMINALS CONNECTED TO RECEIVE A UNIQUE COMBINATION OF THREE OF SAID INPUT SIGNALS; MEANS COMBINING THE OUTPUTS OF SAID FIRST SET OF COINCIDENCE GATES TO PROVIDE AN OUTPUT SIGNAL REPRESENTING THE LOGIC "OR" FUNCTION; INVERTER MEANS FOR INVERTING THE "OR" OUTPUT SIGNAL; A SECOND SET OF COINCIDENCE GATES EACH HAVING AT LEAST THREE INPUT TERMINALS CONNECTED TO RECEIVE A UNIQUE COMBINATION OF THREE SIGNALS FROM AMONG THE REMAINING ONES OF SAID INPUT SIGNALS, SAID "OR" OUTPUT SIGNAL, AND THE INVERTED "OR" OUTPUT SIGNAL;
Claim 2
Dependent Claim
144 words
A LOGIC CIRCUIT FOR INDICATING THE PARITY OF A SET OF BINARY BITS COMPRISING: MEANS SUPPLYING INPUT SIGNALS REPRESENTING SAID BITS AND THE COMPLEMENTS OF SAID BITS, A SIGNAL REPRESENTING A BINARY "1" HAVING A FIRST VALUE AND A SIGNAL REPRESENTING A BINARY "O" HAVING A SECOND, DIFFERENT VALUE; A FIRST SET OF COINCIDENCE GATES EACH HAVING AT LEAST THREE INPUT TERMINALS CONNECTED TO RECEIVE A UNIQUE COMBINATION OF THREE OF SAID INPUT SIGNALS; MEANS COMBINING THE OUTPUTS OF SAID FIRST SET OF COINCIDENCE GATES TO PROVIDE AN OUTPUT SIGNAL REPRESENTING THE LOGIC "OR" FUNCTION; INVERTER MEANS FOR INVERTING THE "OR" OUTPUT SIGNAL; A SECOND SET OF COINCIDENCE GATES EACH HAVING AT LEAST THREE INPUT TERMINALS CONNECTED TO RECEIVE A UNIQUE COMBINATION OF THREE SIGNALS FROM AMONG THE REMAINING ONES OF SAID INPUT SIGNALS, SAID "OR" OUTPUT SIGNAL, AND THE INVERTED "OR" OUTPUT SIGNAL;
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1967-06-09 | 1967-12-09 | 1968-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1971-06-09 | 1971-12-09 | 1972-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1975-06-09 | 1975-12-09 | 1976-06-09 | $7700.00 | Window Closed / Lapsed |