Universal automatic computer utilizing binary coded alphanumeric characters

Claim 1

THE COMBINATION COMPRISING A FULL BINARY ADDER FOR OPERATING ON TRAINS OF ELECTRICAL SIGNALS REPRESENTATIVE OF ALPHABETICAL AND NUMERICAL INFORMATION; EACH OF SAID TRAINS COMPRISING A FIRST GROUP OF PULSE POSITION REPRESENTING BY THE COMBINATIONS OF PULSES PRESENT AND ABSENT IN INDIVIDUAL POSITIONS OF SAID GROUP INFORMATION OF DIFFERENT RELATIVE VALUES AND A SECOND GROUP OF PULSE POSITIONS INDENTIFYING BY THE ABSENCE OF PULSES THEREFROM INFORMATION REPRESENTED BY SAID FIRST GROUP AS NUMERICAL AND IDENTIFYING BY THE PRESENCE OF PULSES THEREIN THE INFORMATION REPRESENTED BY SAID FIRST GROUP AS ALPAHABETICAL SAID ADDER HAVING A FIRST INPUT, A SECOND INPUT, AND AN OUTPUT; MEANS FOR APPLYING A FIRST TRAIN OF ELECTRICAL SIGNALS TO SAID FIRST INPUT; MEANS FOR APPLYING A SECOND TRAIN OF ELECTRICAL SIGNALS TO SAID SECOND INPUT; A BYPASS NETWORK CONNECTING SAID INPUTS AND SAID OUTPUT; A FIRST MEANS INTERPOSED BETWEEN SAID FIRST INPUT OF THE ADDER AND SAID BYPASS NETWORK FOR DETECTING THE PRESENCE OF PULSES IN THE SECOND GROUP OF PULSE POSITIONS IN FIRST TRAINS OF ELECTRICAL SIGNALS APPLIED TO SAID FIRST INPUT TO CASE SAID FIRST TRAINS OF SIGNALS TO BE BYPASSED AROUND SAID ADDER; AND A SECOND MEANS INTERPOSED BETWEEN SAID SECOND INPUT OF THE ADDER AND SAID BYPASS NETWORK FOR DETECTING THE PRESENCE OF PULSES IN THE SECOND GROUP OF PULSE POSITIONS IN SECOND TRAINS OF ELECTRICAL SIGNALS APPLIED TO SAID SECOND INPUT TO CAUSE SAID SECOND TRAINS OF SIGNALS TO BE BYPASSED AROUND SAID ADDER.