Redundancy tranistor triggering circuits

Claim 1

A TRIGGER CIRCUIT, INCLUDING, TWO TRANSISTOR QUADS EACH INCLUDING FOUR TRANSISTORS, EACH OF THE FOUR TRANSISTORS IN EACH TRANSISTOR QUAD HAVING A BASE ELECTRODE, AN EMITTER ELECTRODE AND A COLLECTOR ELECTRODE AND HAVING CONDUCTIVE AND NONCONDUCTIVE STATES, MEANS DIRECTLY CONNECTING THE EMITTER ELECTRODES OF A FIRST PAIR OF THE TRANSISTORS IN EACH QUAD TO EACH OTHER AND TO THE COLLECTOR ELECTRODES OF THE SECOND PAIR OF THE TRANSISTORS IN THE SAME QUAD, BIASING MEANS COUPLED TO THE BASE ELECTRODES OF EACH OF THE FOUR TRANSISTORS IN BOTH QUADS TO BIAS THE TRANSISTORS IN A PARTICULAR ONE OF THE CONDUCTIVE AND NONCONDUCTIVE STATES, BIASING MEANS COUPLED TO THE COLLECTOR ELECTRODES OF THE FIRST PAIR OF TRANSISTORS IN BOTH QUADS TO BIAS THE TRANSISTORS TO THE CONDUCTIVE STATES, AND CIRCUIT MEANS COUPLING THE COLLECTOR ELECTRODES OF THE FIRST PAIR OF TRANSISTORS IN AT LEAST ONE QUAD TO THE BASE ELECTRODES OF ALL FOUR TRANSISTORS IN THE OTHER QUAD TO PROVIDE A STATE OF CONDUCTIVITY IN THE TRANSISTORS IN ONE QUAD AND TO PROVIDE A STATE OF NONCONDUCTIVITY IN THE TRANSISTORS IN THE OTHER QUAD, THE CIRCUIT MEANS INCLUDING A PAIR OF SERIALLY CONNECTED CAPACITORS AND A DIODE IN SERIES WITH THE SERIALLY CONNECTED CAPACITORS AND HAVING A LONGER TIME CONSTANT THAN THE ASSOCIATED TRANSISTORS.