Ring counter with unique gating for self correction

Claim 1

A RING COUNTER COMPRISING A PLURALITY OF BISTABLE DEVICES EACH HAVING A FIRST AND A SECOND STABLE STATE WITH A FIRST AND A SECOND INPUT AND A FIRST AND A SECOND OUTPUT; A CONTROL BISTABLE DEVICE HAVING A FIRST AND A SECOND STABLE STATE WITH A FIRST AND SECOND INPUT AND A FIRST AND A SECOND OUTPUT, A FIRST SOURCE OF RECURRING PULSES CONNECTED TO THE SECOND INPUT OF THE CONTROL BISTABLE DEVICE AND THE SECOND INPUTS OF EACH OF THE BISTABLE DEVICES OF SAID PLURALITY, A CONNECTION FROM THE FIRST OUTPUT OF THE CONTROL BISTABLE DEVICE TO THE FIRST INPUT OF THE FIRST BISTABLE DEVICE OF SAID PLURALITY; A COINCIDENCE GATING MEANS, A SECOND SOURCE OF RECURRING PULSES CONNECTED TO ONE INPUT OF THE GATING MEANS, CONNECTIONS FROM THE SECOND OUTPUT OF EACH OF THE BISTABLE DEVICES EXCEPT THE LAST BISTABLE DEVICE TO THE FIRST INPUT OF THE SUCCEEDING BISTABLE DEVICE AND TO THE REMAINING INPUTS OF THE GATING MEANS; A CONNECTION FROM THE OUTPUT OF THE GATING MEANS TO THE FIRST INPUT OF THE CONTROL BISTABLE DEVICE TO SET THE CONTROL BISTABLE DEVICE TO THE FIRST STATE ONLY IN RESPONSE TO THE PLURALITY OF BISTABLE DEVICES EXCEPT THE LAST BISTABLE DEVICE BEING IN THE SECOND STABLE STATE, WHEREBY ANY ERROR IN THE COUNTER IS ELIMINATED WITHIN ONE CYCLE OF THE COUNTER.