Memory circuit with positive and negative limiters

Claim 1

A VOLTAGE LIMITER SYSTEM FOR A MEMORY CIRCUIT COMPRISING IN COMBINATION, MEANS FOR STORING A MEMORY VOLTAGE, AN AMPLIFIER COUPLED IN PARALLEL WITH SAID MEMORY VOLTAGE STORING MEANS, A VOLTAGE DIVIDER NETWORK CONNECTED BETWEEN THE INPUT OF SAID AMPLIFIER AND GROUND, SAID VOLTAGE DIVIDER NETWORK INCLUDING A PAIR OF SERIES CONNECTED RESISTORS ONE OF WHICH HAS A LARGE RESISTANCE COMPARED TO THE RESISTANCE OF THE OTHER, MEANS COUPLED TO THE OUTPUT OF SAID AMPLIFIER CHANNEL FOR PREVENTING THE UNDUE ELECTRICAL LOADING THEREOF, A TRIO OF TRIODE STAGES CASCADED BETWEEN THE OUTPUT OF SAID AMPLIFIER CHANNEL AND THE JUNCTION OF THE SERIES CONNECTED RESISTORS OF SAID VOLTAGE DIVIDER NETWORK FOR LIMITING THE POSITIVE DEVIATION OF SAID MEMORY VOLTAGE FROM A PREDETERMINED VOLTAGE LEVEL, AND MEANS INTERCONNECTING SAID JUNCTION OF THE SERIES CONNECTED RESISTORS OF SAID VOLTAGE DIVIDER NETWORK AND THE AFORESAID UNDUE ELECTRICAL LOADING PREVENTION MEANS FOR LIMITING THE NEGATIVE DEVIATION OF SAID MEMORY VOLTAGE FROM SAID PREDETERMINED VOLTAGE LEVEL.