Patent US2817205A successfully refreshed from Google Patents.
Patent US3094613A successfully refreshed from Google Patents.
US3094613A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Binary full adder utilizing asymmetric p-n-p-n transistors operated at different saturation current levels
Assignee: International Business Machines Corp
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Filing: 1959-12-17
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Granted: 1963-06-18
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Expires: 1979-12-17
Abstract
No abstract record available.
Inventors
- 👤 Solomon L Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:38
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/5013; G06F2207/00; G06F2207/38; G06F2207/48; G06F2207/4802; G06F2207/4818
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
102 words
A FULL ADDER CIRCUIT COMPRISING A FIRST SEMICONDUCTOR TRANSISTOR STRUCTURE HAVING AN EMITTER, A COLLECTOR, AND A BASE WHICH EXHIBITS A CURRENT MULTIPLICATION FACTOR ALPHA GREATER THAN 1, A SECOND SEMI-CONDUCTOR TRANSISTOR STRUCTURE HAVING AN EMITTER, A COLLECTOR, AND A BASE WHICH EXHIBITS A CURRENT MULTIPLICATION FACTOR ALPHA GREATER THAN 1, SAID FIRST TRANSISTOR HAVING AN ALPHA SLIGHTLY GREATER THAN THE ALPHA OF SAID SECOND TRANSISTOR FIRST AND SECOND OUTPUT IMPEDANCE MEANS RESPECTIVELY COUPLING THE COLLECTORS OF SAID FIRST AND SECOND TRANSISTOR STRUCTURES TO A VOLTAGE BIASING SOURCE, WITH THE RELATIVE MAGNITUDES OF SAID FIRST AND SECOND OUTPUT IMPEDANCE MEANS BEING SUCH
Claim 2
Dependent Claim
102 words
A FULL ADDER CIRCUIT COMPRISING A FIRST SEMICONDUCTOR TRANSISTOR STRUCTURE HAVING AN EMITTER, A COLLECTOR, AND A BASE WHICH EXHIBITS A CURRENT MULTIPLICATION FACTOR ALPHA GREATER THAN 1, A SECOND SEMI-CONDUCTOR TRANSISTOR STRUCTURE HAVING AN EMITTER, A COLLECTOR, AND A BASE WHICH EXHIBITS A CURRENT MULTIPLICATION FACTOR ALPHA GREATER THAN 1, SAID FIRST TRANSISTOR HAVING AN ALPHA SLIGHTLY GREATER THAN THE ALPHA OF SAID SECOND TRANSISTOR FIRST AND SECOND OUTPUT IMPEDANCE MEANS RESPECTIVELY COUPLING THE COLLECTORS OF SAID FIRST AND SECOND TRANSISTOR STRUCTURES TO A VOLTAGE BIASING SOURCE, WITH THE RELATIVE MAGNITUDES OF SAID FIRST AND SECOND OUTPUT IMPEDANCE MEANS BEING SUCH
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1966-06-17 | 1966-12-17 | 1967-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1970-06-17 | 1970-12-17 | 1971-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1974-06-17 | 1974-12-17 | 1975-06-18 | $7700.00 | Window Closed / Lapsed |