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US3091752A
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Error detection circuit for instruction decoders
Assignee: International Business Machines Corp
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Filing: 1958-12-31
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Granted: 1963-05-28
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Expires: 1978-12-31
Abstract
No abstract record available.
Inventors
- 👤 Richard J Randles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:18
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
162 words
AN ERROR CHECKING CIRCUIT COMPRISING A FIRST REGISTER FOR STORING INSTRUCTION WORDS IN BINARY FORM, A PARITY FLIP-FLOP FOR STORING THE PARITY BIT ASSOCIATED WITH A STORED WORD AND REPRESENTATIVE OF CORRECT INSTRUCTION STORAGE, AND AN ALARM FLIP-FLOP, THE LATTER BEING SET TO ITS ALARMINDICATING STATE AT THE SAME TIME THAT AN INSTRUCTION WORD IS STORED IN SAID FIRST REGISTER AND ITS ASSOCIATED PARITY BIT IS STORED IN SAID PARITY FLIP-FLOP, A FIRST GATING MEANS FOR DECODING IN PULSE FORM THE INSTRUCTION WORD STORED IN SAID FIRST REGISTER, TWO OR CIRCUITS AND A SECOND REGISTER OF BISTABLE ELEMENTS, ONE OR CIRCUIT COUPLED TO SAID FIRST GATING MEANS SO AS TO RECEIVE AS INPUTS THOSE DECODED PULSES THAT REPRESENT AN EVEN PARITY INSTRUCTION AND THE SECOND OR CIRCUIT BEING COUPLED TO SAID FIRST GATING MEANS SO AS TO RECEIVE GATED PULSES REPRESENTATIVE OF AN ODD PARITY INSTRUCTION WORD, SAID SECOND REGISTER BEING COUPLED TO THE OUTPUT CIRCUITS OF SAID FIRST GATING MEANS WHEREBY
Claim 2
Dependent Claim
162 words
AN ERROR CHECKING CIRCUIT COMPRISING A FIRST REGISTER FOR STORING INSTRUCTION WORDS IN BINARY FORM, A PARITY FLIP-FLOP FOR STORING THE PARITY BIT ASSOCIATED WITH A STORED WORD AND REPRESENTATIVE OF CORRECT INSTRUCTION STORAGE, AND AN ALARM FLIP-FLOP, THE LATTER BEING SET TO ITS ALARMINDICATING STATE AT THE SAME TIME THAT AN INSTRUCTION WORD IS STORED IN SAID FIRST REGISTER AND ITS ASSOCIATED PARITY BIT IS STORED IN SAID PARITY FLIP-FLOP, A FIRST GATING MEANS FOR DECODING IN PULSE FORM THE INSTRUCTION WORD STORED IN SAID FIRST REGISTER, TWO OR CIRCUITS AND A SECOND REGISTER OF BISTABLE ELEMENTS, ONE OR CIRCUIT COUPLED TO SAID FIRST GATING MEANS SO AS TO RECEIVE AS INPUTS THOSE DECODED PULSES THAT REPRESENT AN EVEN PARITY INSTRUCTION AND THE SECOND OR CIRCUIT BEING COUPLED TO SAID FIRST GATING MEANS SO AS TO RECEIVE GATED PULSES REPRESENTATIVE OF AN ODD PARITY INSTRUCTION WORD, SAID SECOND REGISTER BEING COUPLED TO THE OUTPUT CIRCUITS OF SAID FIRST GATING MEANS WHEREBY
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1966-05-27 | 1966-11-26 | 1967-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1970-05-27 | 1970-11-26 | 1971-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1974-05-27 | 1974-11-26 | 1975-05-28 | $7700.00 | Window Closed / Lapsed |