Limiting amplifier employing non-saturating transistors for providing inphase squarewave output from distorted wave input

Claim 1

AN AMPLIFIER FOR RECONSTRUCTING AN ALTERNATING CURRENT INPUT SIGNAL SO AS TO PROVIDE AMPLITUDE LIMITED COMPLEMENTARY ALTERNATING CURRENT OUTPUT SIGNALS IN PHASE AT A REFERENCE AXIS WITH SAID INPUT SIGNAL, COMPRISING IN COMBINATION A SUBSTANTIALLY CONSTANT UNIDIRECTIONAL CURRENT SOURCE, A REFERENCE POTENTIAL, FIRST AND SECOND SIGNAL AMPLIFYING CURRENT PATHS COUPLING SAID SOURCE AND SAID POTENTIAL, EACH OF SAID PATHS INCLUDING A TRANSISTOR CONSISTING OF EMITTER, BASE AND COLLECTOR ELECTRODES, SAID CURRENT SOURCE HAVING A PREDETERMINED MAGNITUDE BELOW THE SATURATION CURRENT VALUE OF SAID TRANSISTORS TO NEGATE ANY PHASE DELAYS INHERENT IN THE SATURABLE OPERATION OF SAID TRANSISTORS, MEANS COUPLING THE EMITTER ELECTRODES OF SAID TRANSISTORS TO SAID SOURCE AND PRESENTING A LOW IMPEDANCE TO ALTERNATING CURRENTS BETWEEN SAID EMITTER ELECTRODES, FIRST AND SECOND EQUIVALENT MEANS BIASING THE BASE ELECTRODES OF EACH OF SAID TRANSISTORS ENABLING CONDUCTION TO OCCUR IN THE ABSENCE OF SAID INPUT SIGNAL, EACH OF SAID PATHS ALSO INCLUDING IMPEDANCE MEANS IN CIRCUIT WITH EACH OF SAID TRANSISTORS FOR RENDERING SAID PATHS INCLUDING SAID TRANSISTORS OF SUBSTANTIALLY EQUAL IMPEDANCE IN THE ABSENCE OF SAID INPUT SIGNAL, WHEREBY THE UNIDIRECTIONAL CURRENT FLOW FROM SAID SOURCE IS EQUALLY DIVIDED THROUGH EACH OF SAID PATHS, SAID IMPEDANCE MEANS COMPRISING AN EQUIVALENT RESISTIVE-CAPACITIVE NETWORK, MEANS COUPLING SAID INPUT SIGNAL TO THE BASE ELECTRODE OF ONE OF SAID TRANSISTORS, THE BASE ELECTRODE OF THE OTHER OF SAID TRANSISTORS BEING CONNECTED TO ONE OF SAID BIASING MEANS, SO THAT AS THE AMPLITUDE OF SAID INPUT SIGNAL VARIES WITH RESPECT TO SAID REFERENCE AXIS, THE CURRENT FLOW THROUGH SAID PATHS VARIES IN THE UNSATURATED OPERATING REGION OF SAID TRANSISTORS BETWEEN ZERO AND SAID PREDETERMINED MAGNITUDE, PRODUCING EQUAL AND OPPOSITE CURRENT FLOW DIVISION THROUGH SAID PATHS, SAID CURRENT FLOW BEING IN PHASE AT SAID REFERENCE AXIS WITH SAID INPUT SIGNAL, AND MEANS FOR DERIVING SAID COMPLEMENTARY OUTPUTS FROM THE COLLECTOR ELECTRODES OF SAID TRANSISTORS, THE AMPLITUDE OF SAID OUTPUT SIGNALS BEING LIMITED IN ACCORDANCE WITH THE MAGNITUDE OF SAID SOURCE.