Patent US20140189239A1 successfully refreshed from Google Patents.
US20140189239A1
Active / In Force
US
⏱️ 6.1 years remaining
Processors having virtually clustered cores and cache slices
Assignee: Daedalus Prime LLC
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Filing: 2012-12-28
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Granted: —
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Expires: 2032-12-28
Abstract
Abstract A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
Inventors
- 👤 Herbert H. Hum
- 👤 Brinda Ganesh
- 👤 James R. Vash
- 👤 Ganesh Kumar
- 👤 Leena K. Puthiyedath
- 👤 Scott J. Erlanger
- 👤 Eric J. DeHaemer
- 👤 Adrian C. Moga
- 👤 Michelle M. Sebot
- 👤 Richard L. Carlson
- 👤 David Bubien
- 👤 Eric Delano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:19
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0811; G06F12/084
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
89 words
1 . A processor comprising: a plurality of logical processors each having one or more corresponding lower level caches; a shared higher level cache that is shared by the plurality of logical processors, in which the shared higher level cache includes a distributed cache slice for each of the logical processors; and logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor.
Claim 2
Dependent Claim
89 words
1 . A processor comprising: a plurality of logical processors each having one or more corresponding lower level caches; a shared higher level cache that is shared by the plurality of logical processors, in which the shared higher level cache includes a distributed cache slice for each of the logical processors; and logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor.
Claim 3
Dependent Claim
26 words
2 . The processor of claim 1 , wherein the virtual cluster has a same number of cache slices as another virtual cluster of the processor.
Claim 4
Dependent Claim
38 words
3 . The processor of claim 1 , wherein the virtual cluster includes predominantly proximally physically located logical processors that are closer on average to one another than they are to logical processors of a different virtual cluster.
Claim 5
Dependent Claim
40 words
4 . The processor of claim 1 , wherein the virtual cluster includes predominantly logical processors directly coupled to a common interconnect structure, and wherein another virtual cluster includes predominantly logical processors directly coupled to a different common interconnect structure.
Claim 6
Dependent Claim
20 words
5 . The processor of claim 1 , wherein the virtual cluster has a corresponding cache coherency aware memory controller.
Claim 7
Dependent Claim
42 words
6 . The processor of claim 5 , wherein, if the access misses in the subset of the distributed cache slices in the virtual cluster, the access is initially directed to the cache coherency aware memory controller corresponding to the virtual cluster.
Claim 8
Dependent Claim
33 words
7 . The processor of claim 6 , wherein the cache coherency aware memory controller is to snoop cache slices in one or more other virtual clusters to attempt to service the access.
Claim 9
Dependent Claim
67 words
8 . The processor of claim 1 , wherein the processor has two virtual clusters, wherein each logical processor of each of the two virtual clusters is to be identified by a corresponding logical processor identifier, and wherein a single bit in a corresponding position in each of the logical processor identifiers is to identify which of the two virtual clusters the corresponding logical processor is in.
Claim 10
Dependent Claim
18 words
9 . The processor of claim 8 , wherein the logical processor identifiers are derived from a hash.
Claim 11
Dependent Claim
33 words
10 . The processor of claim 1 , wherein the processor is operable to reduce a power consumption state of the virtual cluster without reducing a power consumption state of another virtual cluster.
Claim 12
Dependent Claim
42 words
11 . The processor of claim 1 , wherein most logical processors of the virtual cluster are directly coupled to a first ring interconnect and at least one logical processor of the virtual cluster is directly coupled to a second ring interconnect.
Claim 13
Dependent Claim
33 words
12 . The processor of claim 1 , wherein the plurality of logical processors are monolithically integrated on a semiconductor substrate, and wherein the plurality of logical processors comprise at least twelve cores.
Claim 14
Dependent Claim
74 words
13 . A method comprising: virtually clustering a plurality of logical processors into a virtual cluster, in which each of the logical processors has one or more corresponding lower level caches; and directing an access that misses in one or more lower level caches corresponding to a logical processor to a subset of distributed cache slices, of a shared higher level cache, that are in a virtual cluster that corresponds to the logical processor.
Claim 15
Dependent Claim
74 words
13 . A method comprising: virtually clustering a plurality of logical processors into a virtual cluster, in which each of the logical processors has one or more corresponding lower level caches; and directing an access that misses in one or more lower level caches corresponding to a logical processor to a subset of distributed cache slices, of a shared higher level cache, that are in a virtual cluster that corresponds to the logical processor.
Claim 16
Dependent Claim
23 words
14 . The method of claim 13 , wherein the virtual cluster has a same number of cache slices as another virtual cluster.
Claim 17
Dependent Claim
38 words
15 . The method of claim 13 , wherein the virtual cluster includes predominantly proximally physically located logical processors that are closer on average to one another than they are to logical processors of a different virtual cluster.
Claim 18
Dependent Claim
44 words
16 . The method of claim 13 , wherein the virtual cluster includes predominantly logical processors that are directly coupled to a common interconnect structure, and wherein another virtual cluster includes predominantly logical processors that are directly coupled to a different common interconnect structure.
Claim 19
Dependent Claim
55 words
17 . The method of claim 13 , wherein the virtual cluster has a corresponding cache coherency aware memory controller, and further comprising, if the access misses in the subset of the distributed cache slices in the virtual cluster, initially directing the access to the cache coherency aware memory controller corresponding to the virtual cluster.
Claim 20
Dependent Claim
32 words
18 . The method of claim 17 , further comprising the cache coherency aware memory controller snooping cache slices in one or more other virtual clusters to attempt to service the access.
Claim 21
Dependent Claim
71 words
19 . The method of claim 13 , wherein the processor has two virtual clusters, wherein each logical processor of each of the two virtual clusters is to be identified by a corresponding logical processor identifier, and further comprising using a single bit that is in a same corresponding position in each of the logical processor identifiers to identify which of the two virtual clusters the corresponding logical processor is in.
Claim 22
Dependent Claim
29 words
20 . The method of claim 13 , further comprising reducing a power consumption state of the virtual cluster without reducing a power consumption state of another virtual cluster.
Claim 23
Dependent Claim
110 words
21 . A system comprising: an interconnect; a processor coupled with the interconnect, the processor including: a plurality of logical processors each having one or more corresponding lower level caches; and a shared higher level cache that is shared by the plurality of logical processors, in which the shared higher level cache includes a distributed cache slice for each of the logical processors; and a dynamic random access memory (DRAM) coupled with the interconnect, the DRAM storing virtual cluster aware software, the virtual cluster aware software operable to preferentially allocate memory for a process running on a logical processor of a virtual cluster from memory corresponding to the virtual cluster.
Claim 24
Dependent Claim
110 words
21 . A system comprising: an interconnect; a processor coupled with the interconnect, the processor including: a plurality of logical processors each having one or more corresponding lower level caches; and a shared higher level cache that is shared by the plurality of logical processors, in which the shared higher level cache includes a distributed cache slice for each of the logical processors; and a dynamic random access memory (DRAM) coupled with the interconnect, the DRAM storing virtual cluster aware software, the virtual cluster aware software operable to preferentially allocate memory for a process running on a logical processor of a virtual cluster from memory corresponding to the virtual cluster.
Claim 25
Dependent Claim
61 words
22 . The system of claim 21 , wherein the virtual cluster aware software, if no memory corresponding to the virtual cluster is available, is operable to preferentially allocate memory for the process from memory corresponding to another virtual cluster in a same physical socket, wherein the system includes another processor in another socket also having a plurality of virtual clusters.
Claim 26
Dependent Claim
48 words
23 . The system of claim 21 , further comprising virtual cluster aware power management software stored in the DRAM, the virtual cluster aware power management software operable to reduce a power consumption state of the virtual cluster without reducing a power consumption state of another virtual cluster.
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