US20030192013A1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for facilitating process-compliant layout optimization
Assignee: Synopsys Inc
•
Filing: 2002-04-05
•
Granted: —
•
Expires: 2022-04-05
Abstract
Abstract One embodiment of the invention provides a system that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size. During operation, the system receives a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout. Next, the system simulates effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout. The system then identifies problem areas in the specification that no not meet a specification. Next, the system moves corresponding shapes in the target layout to produce a new target layout for the integrated circuit, so that a simulated printed image of the new target layout meets the specification.
Inventors
- 👤 Michel Cote
- 👤 Philippe Hurat
- 👤 Christophe Pierrat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 09:36
CPC Classifications
G; G03; G03F; G03F1/00; G03F1/36; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F2119/00; G06F2119/18; Y; Y02; Y02P; Y02P90/00; Y02P90/02
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
112 words
1 . A method for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, comprising: receiving a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of a manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, whereby a simulated printed image of the new target layout meets the specification.
Claim 2
Dependent Claim
112 words
1 . A method for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, comprising: receiving a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of a manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, whereby a simulated printed image of the new target layout meets the specification.
Claim 3
Dependent Claim
50 words
2 . The method of claim 1 , further comprising performing optical proximity correction (OPC) on the new target layout to produce a modified layout, wherein a simulated printed image of modified layout more closely matches the new target layout than the simulated printed image of the new target layout.
Claim 4
Dependent Claim
21 words
3 . The method of claim 1 , wherein moving the corresponding shapes in the target layout involves optimizing process latitude.
Claim 5
Dependent Claim
26 words
4 . The method of claim 1 , wherein moving the corresponding shapes in the target layout involves performing a compaction process to minimize layout size.
Claim 6
Dependent Claim
30 words
5 . The method of claim 4 , wherein moving the corresponding shapes in the target layout involves providing at least one of objectives and constraints to the compaction process.
Claim 7
Dependent Claim
33 words
6 . The method of claim 1 , wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout to improve process latitude.
Claim 8
Dependent Claim
21 words
7 . The method of claim 6 , wherein the relaxed rules include priority values for resolving conflicts between relaxed rules.
Claim 9
Dependent Claim
29 words
8 . The method of claim 1 , wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout.
Claim 10
Dependent Claim
23 words
9 . The method of claim 1 , wherein the effects of the manufacturing process are simulated over a range of manufacturing parameters.
Claim 11
Dependent Claim
26 words
10 . The method of claim 1 , wherein the method further comprises using the simulated printed image to estimate a yield for the target layout.
Claim 12
Dependent Claim
28 words
11 . The method of claim 1 , further comprising using information obtained from examining the simulated printed image to formulate new design rules for the target layout.
Claim 13
Dependent Claim
27 words
12 . The method of claim 1 , wherein the target layout defines a standard cell that is used as a building block for the integrated circuit.
Claim 14
Dependent Claim
29 words
13 . The method of claim 1 , further comprising performing a design rule checking operation on the target layout prior to simulating the effects of the manufacturing process.
Claim 15
Dependent Claim
131 words
14 . A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising: receiving a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, whereby a simulated printed image of the new target layout meets the specification.
Claim 16
Dependent Claim
131 words
14 . A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising: receiving a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, whereby a simulated printed image of the new target layout meets the specification.
Claim 17
Dependent Claim
55 words
15 . The computer-readable storage medium of claim 14 , wherein the method further comprises performing optical proximity correction (OPC) on the new target layout to produce a modified layout, wherein a simulated printed image of modified layout more closely matches the new target layout than the simulated printed image of the new target layout.
Claim 18
Dependent Claim
27 words
16 . The computer-readable storage medium of claim 14 , wherein moving the corresponding shapes in the target layout involves optimizing process latitude for the target layout.
Claim 19
Dependent Claim
28 words
17 . The computer-readable storage medium of claim 14 , wherein moving the corresponding shapes in the target layout involves performing a compaction process to minimize layout size.
Claim 20
Dependent Claim
28 words
18 . The computer-readable storage medium of claim 17 , wherein moving the corresponding shapes in the target layout involves providing objectives and/or constraints to the compaction process.
Claim 21
Dependent Claim
35 words
19 . The computer-readable storage medium of claim 14 , wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout to improve process latitude.
Claim 22
Dependent Claim
23 words
20 . The computer-readable storage medium of claim 19 , wherein the relaxed rules include priority values for resolving conflicts between relaxed rules.
Claim 23
Dependent Claim
31 words
21 . The computer-readable storage medium of claim 14 , wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout.
Claim 24
Dependent Claim
25 words
22 . The computer-readable storage medium of claim 14 , wherein the effects of the manufacturing process are simulated over a range of manufacturing parameters.
Claim 25
Dependent Claim
28 words
23 . The computer-readable storage medium of claim 14 , wherein the method further comprises using the simulated printed image to estimate a yield for the target layout.
Claim 26
Dependent Claim
33 words
24 . The computer-readable storage medium of claim 14 , wherein the method further comprises using information obtained from examining the simulated printed image to formulate new design rules for the target layout.
Claim 27
Dependent Claim
29 words
25 . The computer-readable storage medium of claim 14 , wherein the target layout defines a standard cell that is used as a building block for the integrated circuit.
Claim 28
Dependent Claim
34 words
26 . The computer-readable storage medium of claim 14 , wherein the method further comprises performing a design rule checking operation on the target layout prior to simulating the effects of the manufacturing process.
Claim 29
Dependent Claim
135 words
27 . An apparatus for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, comprising: a receiving mechanism that is configured to receive a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; a simulation mechanism that is configured to simulate effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; and an optimization mechanism that is configured to, identify problem areas in the simulated printed image that do not meet a specification, and to move corresponding shapes in the target layout to produce new target layout for the integrated circuit, whereby a simulated printed image of the new target layout meets the specification.
Claim 30
Dependent Claim
135 words
27 . An apparatus for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, comprising: a receiving mechanism that is configured to receive a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; a simulation mechanism that is configured to simulate effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; and an optimization mechanism that is configured to, identify problem areas in the simulated printed image that do not meet a specification, and to move corresponding shapes in the target layout to produce new target layout for the integrated circuit, whereby a simulated printed image of the new target layout meets the specification.
Claim 31
Dependent Claim
57 words
28 . The apparatus of claim 27 , further comprising an optical proximity correction (OPC) mechanism that is configured to perform OPC on the new target layout to produce a modified layout, wherein a simulated printed image of modified layout more closely matches the new target layout than the simulated printed image of the new target layout.
Claim 32
Dependent Claim
22 words
29 . The apparatus of claim 27 , wherein the optimization mechanism is configured to optimize process latitude for the target layout.
Claim 33
Dependent Claim
23 words
30 . The apparatus of claim 27 , wherein the optimization mechanism is configured to perform a compaction process to minimize layout size.
Claim 34
Dependent Claim
32 words
31 . The apparatus of claim 30 , wherein the optimization mechanism is configured to move the corresponding shapes in the target layout by providing objectives and/or constraints to the compaction process.
Claim 35
Dependent Claim
30 words
32 . The apparatus of claim 27 , wherein the optimization mechanism is configured to apply relaxed rules to the problem areas of the target layout to improve process latitude.
Claim 36
Dependent Claim
21 words
33 . The apparatus of claim 32 , wherein the relaxed rules include priority values for resolving conflicts between relaxed rules.
Claim 37
Dependent Claim
26 words
34 . The apparatus of claim 27 , wherein the optimization mechanism is configured to apply relaxed rules to the problem areas of the target layout.
Claim 38
Dependent Claim
27 words
35 . The apparatus of claim 27 , wherein the simulation mechanism is configured to simulate effects of the manufacturing process over a range of manufacturing parameters.
Claim 39
Dependent Claim
24 words
36 . The apparatus of claim 27 , wherein the optimization mechanism is additionally configured to estimate a yield f or the target layout.
Claim 40
Dependent Claim
33 words
37 . The apparatus of claim 27 , wherein the optimization mechanism is configured to use information obtained from examining the simulated printed image to formulate new design rules for the target layout.
Claim 41
Dependent Claim
27 words
38 . The apparatus of claim 27 , wherein the target layout defines a standard cell that is used as a building block for the integrated circuit.
Claim 42
Dependent Claim
38 words
39 . The apparatus of claim 27 , further comprising a design rule checking mechanism that is configured to perform a design rule checking operation on the target layout prior feeding the target layout to the simulation mechanism.
Claim 43
Dependent Claim
130 words
40 . A mask to be used in an optical lithography process, wherein the mask is created through a method that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising: receiving a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein a simulated printed image of the new target layout meets the specification.
Claim 44
Dependent Claim
130 words
40 . A mask to be used in an optical lithography process, wherein the mask is created through a method that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising: receiving a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein a simulated printed image of the new target layout meets the specification.
Claim 45
Dependent Claim
119 words
41 . An integrated circuit created through a method that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising: receiving a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein a simulated printed image of the new target layout meets the specification.
Claim 46
Dependent Claim
119 words
41 . An integrated circuit created through a method that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising: receiving a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein a simulated printed image of the new target layout meets the specification.
References Cited (Backward Citations)
US5021847A
Cited
US6425117B1
Cited
US5812412A
Cited
US5680588A
Cited
US5725974A
Cited
US6470489B1
Cited
US6425112B1
Cited
US6577994B1
Cited
US20020152453A1
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.