Computer aided design system and computer-readable medium storing a program for designing clock gated logic circuits and gated clock circuit

Claim 2

1 . A gated clock circuit comprising: a plurality of storage elements which are grouped into a plurality of partial trees; a plurality of gating circuits provided respectively for said partial trees in order to control the supply of a clock signal to each of said partial trees respectively in accordance with the logic sum of the enable logics of those of said storage elements belonging to said each of said partial trees, wherein at least one of said partial trees has at least one of said storage elements having a feedback loop and at least one of said storage elements having no feedback loop.

Claim 3

2 . The gated clock circuit as claimed in claim 1 wherein said storage elements are grouped into the plurality of partial trees in order that the disparity in the numbers of said storage elements belonging to said partial trees is no higher than 5%

Claim 4

3 . The gated clock circuit as claimed in claim 1 wherein said storage elements are register circuits consisting of flip-flops.

Claim 5

4 . The gated clock circuit as claimed in claim 3 wherein said feedback loop is composed of a multiplexer for selecting either of the output signal of said register circuit and the external input signal and outputting the signal as selected to said register circuit in accordance with the enable logic of the group including the storage element having that feedback loop.

Claim 6

5 . A computer aided design system for clock gated logic circuits consisting of a plurality of storage elements, said system comprising: a circuit information storing section for storing information about a clock gated logic circuit under the design; a storage element allocation section for allocating said storage elements to a plurality of partial trees on the basis of said information about a clock gated logic circuit said gated clock circuit under the design; an output section for outputting clock tree structure information with gating logics under the design on the basis of said partial trees consisting of said storage elements as allocated by said storage element allocation section; wherein at least one of said partial trees has at least one of said storage elements having a feedback loop and at least one of said storage elements having no feedback loop.

Claim 7

5 . A computer aided design system for clock gated logic circuits consisting of a plurality of storage elements, said system comprising: a circuit information storing section for storing information about a clock gated logic circuit under the design; a storage element allocation section for allocating said storage elements to a plurality of partial trees on the basis of said information about a clock gated logic circuit said gated clock circuit under the design; an output section for outputting clock tree structure information with gating logics under the design on the basis of said partial trees consisting of said storage elements as allocated by said storage element allocation section; wherein at least one of said partial trees has at least one of said storage elements having a feedback loop and at least one of said storage elements having no feedback loop.

Claim 8

6 . The computer aided design system for clock gated logic circuits as claimed in claim 5 wherein said circuit information storing section serves to store clock tree structure information without gating logics as said information about the clock gated logic circuit under the design.

Claim 9

7 . The computer aided design system for clock gated logic circuits as claimed in claim 5 wherein said storage elements are allocated to the plurality of partial trees in order that the disparity in the numbers of said storage elements belonging to said partial trees is no higher than 5%

Claim 10

8 . The computer aided design system for clock gated logic circuits as claimed in claim 5 wherein said gating logics are provided to control the supply of the clock signal to said partial trees in accordance with the logic sum of the enable logics of those of said storage elements belonging to said each of said partial trees.

Claim 11

9 . The computer aided design system for clock gated logic circuits as claimed in claim 5 wherein, while said storage element allocation section serves to generate a plurality of allocation patterns according to each of which said storage element are allocated to said partial trees in a different manner, said output section serves to output one of said allocation patterns taking into consideration the electric power consumption of the gated clock circuit as constructed in accordance with each allocation pattern.

Claim 12

10 . A computer program embodied on a computer-readable medium for designing clock gated logic circuits, said program comprising: a step of obtaining information about a clock gated logic circuit under the design; a step of allocating said storage elements to a plurality of partial trees on the basis of said information about a clock gated logic circuit said gated clock circuit under the design; a step of outputting clock tree structure information with gating logics under the design on the basis of said partial trees consisting of said storage elements as allocated by said allocating step, wherein at least one of said partial trees has at least one of said storage elements having a feedback loop and at least one of said storage elements having no feedback loop.

Claim 13

10 . A computer program embodied on a computer-readable medium for designing clock gated logic circuits, said program comprising: a step of obtaining information about a clock gated logic circuit under the design; a step of allocating said storage elements to a plurality of partial trees on the basis of said information about a clock gated logic circuit said gated clock circuit under the design; a step of outputting clock tree structure information with gating logics under the design on the basis of said partial trees consisting of said storage elements as allocated by said allocating step, wherein at least one of said partial trees has at least one of said storage elements having a feedback loop and at least one of said storage elements having no feedback loop.

Claim 14

11 . A computer program embodied on a computer-readable medium as claimed in claim 10 wherein said information about the clock gated logic circuit under the design includes clock tree structure information without gating logics.

Claim 15

12 . A computer program embodied on a computer-readable medium as claimed in claim 10 wherein said storage elements are allocated to the plurality of partial trees in order that the disparity in the numbers of said storage elements belonging to said partial trees is no higher than 5%.

Claim 16

13 . The computer program embodied on a computer-readable medium as claimed in claim 10 wherein said gating logics are provided to control the supply of the clock signal to said partial trees in accordance with the logic sum of the enable logics of those of said storage elements belonging to said each of said partial trees.

Claim 17

14 . The computer program embodied on a computer-readable medium as claimed in claim 10 wherein, while a plurality of allocation patterns are generated, according to each of which patterns said storage element are allocated to said partial trees,in a different manner, one of said allocation patterns is selectively output, taking into consideration the electric power consumption of the gated clock circuit as constructed in accordance with each allocation pattern.