US6020774A
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Gated clock tree synthesis method for the logic design
Assignee: Via Technologies Inc
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Filing: 1998-07-23
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Granted: 2000-02-01
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Expires: 2018-07-23
Abstract
Abstract A gated clock tree synthesis (CTS) method is provided for the purpose of synthesizing a gate array logic circuit to allow optimal topological arrangement of the gate array on the logic circuit. This in turn allows the logic circuit to operate more efficiently. The logic circuit includes at least one clock generator, a plurality of control gates each having one input end connected to a control signal and the other input end connected to receive the output clock signal from the clock generator, a plurality of first logic elements that are directly driven by the output clock signal from the clock generator, and a plurality of second logic elements that are driven by the gated clock signal outputted from each of the control gates under control by the control signal. The gated CTS method comprises the steps of grouping the first logic elements into a plurality of groups, connecting each group of the first logic elements via a first buffer to one of the control gates, connecting each of the second logic elements via a second buffer to the clock generator, and connecting one input end of each of the control gates to the clock generator.
Inventors
- 👤 You-Ming Chiu
- 👤 Jiin Lai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:33
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F30/00; G06F30/30; G06F30/32; G06F30/327; G06F30/39; G06F30/396; G06F2117/00; G06F2117/04
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
188 words
A gated CTS method for synthesizing a logic circuit including at least one clock generator, a plurality of control gates each having one input end connected to a control signal and the other input end connected to receive the output clock signal from the clock generator, a plurality of first logic elements driven directly by the output clock signal from the clock generator, and a plurality of second logic elements that are driven by the gated clock signal that is outputted from each of the control gates under control of the control signal, the gated CTS method comprising the steps of: (1) grouping the first logic elements according to whether they are driven by a gated version of the clock signal from the clock generator or a non-gated version of the clock signal from the clock generator; (2) connecting each group of the first logic elements via a first buffer to one of the control gates; (3) connecting each of the second logic elements via a second buffer to the clock generator; and (4) connecting one input end of each of the control gates to the clock generator.
Claim 2
Dependent Claim
188 words
A gated CTS method for synthesizing a logic circuit including at least one clock generator, a plurality of control gates each having one input end connected to a control signal and the other input end connected to receive the output clock signal from the clock generator, a plurality of first logic elements driven directly by the output clock signal from the clock generator, and a plurality of second logic elements that are driven by the gated clock signal that is outputted from each of the control gates under control of the control signal, the gated CTS method comprising the steps of: (1) grouping the first logic elements according to whether they are driven by a gated version of the clock signal from the clock generator or a non-gated version of the clock signal from the clock generator; (2) connecting each group of the first logic elements via a first buffer to one of the control gates; (3) connecting each of the second logic elements via a second buffer to the clock generator; and (4) connecting one input end of each of the control gates to the clock generator.
Claim 3
Dependent Claim
14 words
The method of claim 1, wherein each the first logic element is a flip-flop.
Claim 4
Dependent Claim
14 words
The method of claim 1, wherein each the first logic element is a latch.
Claim 5
Dependent Claim
13 words
The method of claim 1, wherein each second logic element is a flip-flop.
Claim 6
Dependent Claim
14 words
The method of claim 1, wherein each the second logic element is a latch.
Claim 7
Dependent Claim
14 words
The method of claim 1, wherein each the control gate is an AND gate.
Claim 8
Dependent Claim
14 words
The method of claim 1, wherein each the control gate is an OR gate.
Claim 9
Dependent Claim
139 words
A gated CTS method for synthesizing a logic circuit which requires a number of gated clock signals and non-gated clock signals to operate, the gated clock signals each being enabled by a corresponding control signal, the method comprising the steps of: (1) connecting each control signal to a corresponding control gate; (2) grouping a plurality of first logic elements according to whether driven by a gated version of the clock signal from the clock generator or a non-gated version of the clock signal from the clock generator; (3) connecting each group of the first logic elements via a first buffer to one of the control gates; (4) connecting each of a plurality of second logic elements via a second buffer to the clock generator; and (5) connecting one input end of each the control gate to the clock generator.
Claim 10
Dependent Claim
139 words
A gated CTS method for synthesizing a logic circuit which requires a number of gated clock signals and non-gated clock signals to operate, the gated clock signals each being enabled by a corresponding control signal, the method comprising the steps of: (1) connecting each control signal to a corresponding control gate; (2) grouping a plurality of first logic elements according to whether driven by a gated version of the clock signal from the clock generator or a non-gated version of the clock signal from the clock generator; (3) connecting each group of the first logic elements via a first buffer to one of the control gates; (4) connecting each of a plurality of second logic elements via a second buffer to the clock generator; and (5) connecting one input end of each the control gate to the clock generator.
Claim 11
Dependent Claim
14 words
The method of claim 8, wherein each the first logic element is a flip-flop.
Claim 12
Dependent Claim
14 words
The method of claim 8, wherein each the second logic element is a latch.
Claim 13
Dependent Claim
14 words
The method of claim 8, wherein each the second logic element is a flip-flop.
Claim 14
Dependent Claim
14 words
The method of claim 8, wherein each the second logic element is a latch.
Claim 15
Dependent Claim
14 words
The method of claim 8, wherein each the control gate is an AND gate.
Claim 16
Dependent Claim
14 words
The method of claim 8, wherein each the control gate is an OR gate.
Claim 17
Dependent Claim
145 words
A gated clock tree synthesized logic circuit, which comprises: at least one clock generator for generating a clock signal; a plurality of control gates each having one input end connected to a control signal and the other input end connected to receive the output clock signal from the clock generator; a plurality of first buffers, each having an input end connected to receive the gated clock signal from each of the control gates; at least one second buffer having an input end connected to receive the clock signal from the clock generator; a plurality of first logic elements, coupled respectively to the first buffers so as to be driven by the gated clock signal buffered by the first buffers; and a plurality of second logic elements, coupled to the second buffer so as to be driven by the clock signal buffered by the second buffer.
Claim 18
Dependent Claim
145 words
A gated clock tree synthesized logic circuit, which comprises: at least one clock generator for generating a clock signal; a plurality of control gates each having one input end connected to a control signal and the other input end connected to receive the output clock signal from the clock generator; a plurality of first buffers, each having an input end connected to receive the gated clock signal from each of the control gates; at least one second buffer having an input end connected to receive the clock signal from the clock generator; a plurality of first logic elements, coupled respectively to the first buffers so as to be driven by the gated clock signal buffered by the first buffers; and a plurality of second logic elements, coupled to the second buffer so as to be driven by the clock signal buffered by the second buffer.
Claim 19
Dependent Claim
15 words
The logic circuit of claim 15, wherein each the first logic element is a flip-flop.
Claim 20
Dependent Claim
15 words
The logic circuit of claim 15, wherein each the first logic element is a latch.
Claim 21
Dependent Claim
15 words
The logic circuit of claim 15, wherein each the second logic element is a flip-flop.
Claim 22
Dependent Claim
15 words
The logic circuit of claim 15, wherein each the second logic element is a latch.
Claim 23
Dependent Claim
15 words
The logic circuit of claim 15, wherein each the control gate is an AND gate.
Claim 24
Dependent Claim
15 words
The logic circuit of claim 15, wherein each the control gate is an OR gate.
Claim 25
Dependent Claim
159 words
A gated CTS method for synthesizing a logic circuit which is driven by a system clock signal and requires a number of gated versions of the system clock signal and non-gated versions of the system clock signal to operate, each of the gated clock signals being enabled by a corresponding control signal, the method comprising the steps of: (1) connecting each control signal to a corresponding control gate; (2) grouping a plurality of first logic elements according to whether driven by a gated version of the clock signal from the clock generator or a non-gated version of the clock signal from the clock generator; (3) connecting each group of the first logic elements via a first buffer to one of the control gates; (4) connecting each of a plurality of second logic elements via a second buffer to the system clock signal; and (5) connecting one input end of each of the control gates to the system clock signal.
Claim 26
Dependent Claim
159 words
A gated CTS method for synthesizing a logic circuit which is driven by a system clock signal and requires a number of gated versions of the system clock signal and non-gated versions of the system clock signal to operate, each of the gated clock signals being enabled by a corresponding control signal, the method comprising the steps of: (1) connecting each control signal to a corresponding control gate; (2) grouping a plurality of first logic elements according to whether driven by a gated version of the clock signal from the clock generator or a non-gated version of the clock signal from the clock generator; (3) connecting each group of the first logic elements via a first buffer to one of the control gates; (4) connecting each of a plurality of second logic elements via a second buffer to the system clock signal; and (5) connecting one input end of each of the control gates to the system clock signal.
Claim 27
Dependent Claim
14 words
The method of claim 22, wherein each the first logic element is a flip-flop.
Claim 28
Dependent Claim
14 words
The method of claim 22, wherein each the first logic element is a latch.
Claim 29
Dependent Claim
14 words
The method of claim 22, wherein each the second logic element is a flip-flop.
Claim 30
Dependent Claim
14 words
The method of claim 22, wherein each the second logic element is a latch.
Claim 31
Dependent Claim
14 words
The method of claim 22, wherein each the control gate is an AND gate.
Claim 32
Dependent Claim
14 words
The method of claim 22, wherein each the control gate is an OR gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-31 | 2003-08-02 | 2004-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-31 | 2007-08-02 | 2008-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-31 | 2011-08-02 | 2012-02-01 | $7700.00 | Window Closed / Lapsed |