US20030109967A1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Operating system coordinated thermal management
Assignee: Intel Corp
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Filing: 2001-12-12
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Granted: —
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Expires: 2021-12-12
Abstract
Abstract A processor's performance state may be adjusted based on processor temperature. On transitions to a lower performance state due to the processor getting hotter, the processor's frequency is reduced prior to reducing the processor voltage. Thus, the processor's performance, as seen by the operating system, is reduced immediately. Conversely, on transitions to a higher performance state, due to the processor cooling down, the processor's frequency is not increased until the voltage is changed to a higher level. An interrupt event may be generated anytime the processor's phase locked loop relocks at a new frequency level. Thus, when the interrupt fires, the operating system can read the processor's performance state. As a result, interrupts are not generated that would cause processor performance to lag the interrupt event.
Inventors
- 👤 Barnes Cooper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:29
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; G06F1/16; G06F1/20; G06F1/206; G06F1/3296; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
30 words
1 . A method comprising: detecting that a processor's frequency has changed in response to processor cooling; and generating an interrupt in response to the detection of the frequency change.
Claim 2
Dependent Claim
30 words
1 . A method comprising: detecting that a processor's frequency has changed in response to processor cooling; and generating an interrupt in response to the detection of the frequency change.
Claim 3
Dependent Claim
15 words
2 . The method of claim 1 including providing an interrupt to an operating system.
Claim 4
Dependent Claim
20 words
3 . The method of claim 1 including reading the performance state of the processor in response to the interrupt.
Claim 5
Dependent Claim
13 words
4 . The method of claim 3 including determining a new performance state.
Claim 6
Dependent Claim
12 words
5 . The method of claim 4 including scheduling a bandwidth allocation.
Claim 7
Dependent Claim
13 words
6 . The method of claim 2 including setting up a periodic timer.
Claim 8
Dependent Claim
15 words
7 . The method of claim 6 including monitoring the processor temperature at periodic intervals.
Claim 9
Dependent Claim
37 words
8 . The method of claim 1 including detecting a high temperature or a low temperature interrupt and reading the processor performance state in response to the detection of a high temperature or a low temperature interrupt.
Claim 10
Dependent Claim
20 words
9 . The method of claim 1 wherein detecting a frequency change includes detecting a processor phase locked loop event.
Claim 11
Dependent Claim
12 words
10 . The method of claim 1 including using hardware controlled throttling.
Claim 12
Dependent Claim
40 words
11 . An article comprising a medium storing instructions to enable a processor-based system to: detect that a processor's frequency has changed in response to processor cooling; and generate an interrupt in response to the detection of the frequency change.
Claim 13
Dependent Claim
40 words
11 . An article comprising a medium storing instructions to enable a processor-based system to: detect that a processor's frequency has changed in response to processor cooling; and generate an interrupt in response to the detection of the frequency change.
Claim 14
Dependent Claim
23 words
12 . The article of claim 11 further storing instructions to enable a processor-based system to provide an interrupt to an operating system.
Claim 15
Dependent Claim
28 words
13 . The article of claim 11 further storing instructions to enable a processor-based system to read the performance state of the processor in response to the interrupt.
Claim 16
Dependent Claim
21 words
14 . The article of claim 13 further storing instructions to enable a processor-based system to determine a new performance state.
Claim 17
Dependent Claim
20 words
15 . The article of claim 14 further storing instructions to enable a processor-based system to schedule a bandwidth allocation.
Claim 18
Dependent Claim
21 words
16 . The article of claim 12 further storing instructions to enable a processor-based system to set up a periodic timer.
Claim 19
Dependent Claim
23 words
17 . The article of claim 16 further storing instructions to enable a processor-based system to monitor the processor temperature at periodic intervals.
Claim 20
Dependent Claim
45 words
18 . The article of claim 11 further storing instructions to enable a processor-based system to detect a high temperature or a low temperature interrupt and read the processor performance state in response to the detection of a high temperature or a low temperature interrupt.
Claim 21
Dependent Claim
23 words
19 . The article of claim 11 further storing instructions to enable a processor-based system to detect a processor phase locked loop event.
Claim 22
Dependent Claim
20 words
20 . The article of claim 11 further storing instructions to enable a processor-based system to use hardware controlled throttling.
Claim 23
Dependent Claim
48 words
21 . A system comprising: a processor; a temperature sensor coupled to said processor; and a storage storing instructions that enable the processor to detect that the processor's frequency has changed in response to processor cooling and generate an interrupt in response to detection of the frequency change.
Claim 24
Dependent Claim
48 words
21 . A system comprising: a processor; a temperature sensor coupled to said processor; and a storage storing instructions that enable the processor to detect that the processor's frequency has changed in response to processor cooling and generate an interrupt in response to detection of the frequency change.
Claim 25
Dependent Claim
22 words
22 . The system of claim 21 including a storage storing an operating system, said interrupt being provided to the operating system.
Claim 26
Dependent Claim
29 words
23 . The system of claim 21 wherein said storage stores instructions that enable the processor to read the performance state of the processor in response to an interrupt.
Claim 27
Dependent Claim
15 words
24 . The system of claim 21 wherein said processor determines a new performance state.
Claim 28
Dependent Claim
21 words
25 . The system of claim 24 wherein said storage stores instructions that enable the processor to schedule a bandwidth allocation.
Claim 29
Dependent Claim
22 words
26 . The system of claim 22 wherein said storage stores instructions that enable the processor to set up a periodic timer.
Claim 30
Dependent Claim
24 words
27 . The system of claim 26 wherein said storage stores instructions that enable the processor to monitor the processor temperature at periodic intervals.
Claim 31
Dependent Claim
46 words
28 . The system of claim 21 wherein said storage stores instructions that enable the processor to detect a high temperature or a low temperature interrupt and read the processor performance state in response to the detection of a high temperature or a low temperature interrupt.
Claim 32
Dependent Claim
24 words
29 . The system of claim 21 wherein said storage stores instructions that enable the processor to detect a processor phase locked loop event.
Claim 33
Dependent Claim
11 words
30 . The system of claim 21 including hardware controlled throttling.
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