Patent US20030109104A1 successfully refreshed from Google Patents.
US20030109104A1
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Method for preventing bit line to bit line leakage in memory cell
Assignee: Macronix International Co Ltd
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Filing: 2001-07-16
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Granted: —
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Expires: 2021-07-16
Abstract
Abstract A method for preventing bit line to bit line leakage in memory cell is described. In this method, P-implantation is applied to suppress the leakage current induced by the damage, wherein the damage is caused by the etching step for the formation of spacers. The P-implantation step is performed after the etching step, and such a sequence centralizes the implanted ions to prevent them from decreasing the threshold voltage. On the other hand, the P-implantation step is performed after the bit lines annealing step to prevent the implanted ions from being thermally diffused.
Inventors
- 👤 Chia-Hsing Chen
- 👤 Chen-Chin Liu
- 👤 Jiunn-Liang Li
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:23
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
97 words
1 . A method for preventing bit line to bit line leakage in a memory cell, the method comprising: forming a plurality of word lines having sidewalls on a silicon substrate; depositing a oxide layer on the word lines; etching back the oxide layer to form spacers on the sidewalls of the word lines, whereby the silicon substrate between the word lines is damaged by the etching back; performing an annealing step; and implanting ions into the silicon substrate between the word lines by using the word lines and the spacers as masks after the annealing step.
Claim 2
Dependent Claim
97 words
1 . A method for preventing bit line to bit line leakage in a memory cell, the method comprising: forming a plurality of word lines having sidewalls on a silicon substrate; depositing a oxide layer on the word lines; etching back the oxide layer to form spacers on the sidewalls of the word lines, whereby the silicon substrate between the word lines is damaged by the etching back; performing an annealing step; and implanting ions into the silicon substrate between the word lines by using the word lines and the spacers as masks after the annealing step.
Claim 3
Dependent Claim
85 words
2 . A process for forming a memory cell array, comprising: providing a silicon substrate having a plurality of bit lines thereon; forming a plurality of word lines having sidewalls on the substrate; depositing an oxide layer on the word lines; etching back the oxide layer to form spacers on the sidewalls of the word lines; performing an annealing step; and implanting ions into the silicon substrate between the word lines by using the word lines and the spacers as masks after the annealing step.
Claim 4
Dependent Claim
85 words
2 . A process for forming a memory cell array, comprising: providing a silicon substrate having a plurality of bit lines thereon; forming a plurality of word lines having sidewalls on the substrate; depositing an oxide layer on the word lines; etching back the oxide layer to form spacers on the sidewalls of the word lines; performing an annealing step; and implanting ions into the silicon substrate between the word lines by using the word lines and the spacers as masks after the annealing step.
Claim 5
Dependent Claim
18 words
3 . The process according to claim 2 , wherein the ions are boron or BF 2 ions.
Claim 6
Dependent Claim
18 words
4 . The process according to claim 2 , wherein the oxide layer is a tetra-ethyl-ortho-silicate oxide layer.
Claim 7
Dependent Claim
17 words
5 . The process according to claim 2 , wherein the word lines are made of polysilicon.
Claim 8
Dependent Claim
70 words
6 . A method for suppressing leakage between bit lines on a silicon substrate, wherein a plurality of word lines having sidewalls are formed over the bit lines, and wherein the word lines have oxide spacers on the sidewalls, the improvement comprising: implanting ions into the silicon substrate between word lines by using the word lines and the oxide spacers as masks, thereby suppressing the leakage between the bit lines.
Claim 9
Dependent Claim
70 words
6 . A method for suppressing leakage between bit lines on a silicon substrate, wherein a plurality of word lines having sidewalls are formed over the bit lines, and wherein the word lines have oxide spacers on the sidewalls, the improvement comprising: implanting ions into the silicon substrate between word lines by using the word lines and the oxide spacers as masks, thereby suppressing the leakage between the bit lines.
Claim 10
Dependent Claim
18 words
7 . The method according to claim 6 , further comprising a step of annealing the bit lines.
Claim 11
Dependent Claim
40 words
8 . The method according to claim 7 , wherein the annealing step is performed after the oxide spacers are formed and before the ion implantation step is performed, thereby preventing the ions from being diffused in the annealing step.
Claim 12
Dependent Claim
17 words
9 . The method according to claim 6 , wherein the oxide spacers are tetra-ethyl-ortho-silicate oxide spacers.
Claim 13
Dependent Claim
17 words
10 . The method according to claim 6 , wherein the word lines are made of polysilicon.
References Cited (Backward Citations)
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