Layered floor planar

Abstract

Abstract PURPOSE: To reduce a required chip area by estimating the number of connections between functions through all N levels of a hierarchy and determining the position, on an integrated circuit, of each function of the n-th level within the hierarchy partly on the basis of the estimated number of connections. CONSTITUTION: An integrated circuit (level 1) has a hierarchy of N levels (N>=1) of functions. In the hierarchy, at least one of functions (primary functions) of the n-th level (1<=n<=N) is defined as a plurality of functions of the (n+1)-th level. Each secondary function is a final function, and each final function is connected with another final function through at least one net. Each net defines a plurality of interconnected final functions. Then, the number of connections between functions is estimated through all the N levels of the hierarchy, and the position, on the integrated circuit, of each function of the n-level within the hierarchy is determined partly on the basis of the estimated number of connections.

Inventors

• 👤 Modaresu Hosein
• 👤 Raamu Suuzan
• 👤 Rai Jinhao

Bibliographic Details