Semiconductor device

Abstract

Abstract PURPOSE: To reduce paracitic capacitors largely by reducing the area of a parasitic region and to achieve high performance and high density in a MOSFET, in a semiconductor device having a MIS structure, by providing a polycrystalline silicon layer, which is provided in an element isolating region, providing source regions and drain regions, which have the distribution of impurity concentrations of a gentle inclination, and providing a channel region and a gate electrode, which are determined in a self- aligning manner. CONSTITUTION: Source regions and drain regions, which have the distribution of impurity concentrations of a gentle inclination, are formed in a self-aligning manner by the diffusion of impurities from an N + type polycrystalline silicon layer 5. The lead-out of electrodes is performed with the N + type polycrystalline silicon layer 5. A channel region is determined in a self-aligning manner with the N + type polycrystalline silicon layer 5. A gate electrode 8 is formed through a gate film 6. Since the sources/drains 3, 3a, 4 and 4a are formed in a self-aligning manner by the diffusion of the impurities from the N + type polycrystalline silicon layer 5 and the lead-out of the source/drain electrodes is performed with the N + type polycrystalline silicon layer 5, the size of an element can be reduced without restriction on lithography technology. Thus parasitic elements such as a drain-substrate capacitor are reduce to a large extent. COPYRIGHT: (C)1989,JPO&Japio

Inventors

• 👤 Tomoyuki Furuhata

Bibliographic Details