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JPS647616A Expired / Lapsed JP ⏱️ 0.0 years remaining

Annealing method for iii-v compound semiconductor for short time

Assignee: NEC Corp
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Filing: 1987-06-30
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Granted: —
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Expires: 2007-06-30
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Abstract

Abstract PURPOSE:To suppress the warpage of a substrate and the generation of a slip line on the basis of thermal irregularity in the substrate to very small values by placing the substrate on a quartz glass plate and annealing it for a short time. CONSTITUTION:After ions are implanted to a III-V compound semiconductor single crystalline substrate 3, the substrate 3 is mounted on a quartz glass plate 4, and annealed for a short time. For example, after Si<+> is implanted 5X10<12>cm<-2> by 100KeV of implanting energy at room temperature on an LEC method undoped semi-insulating GaAS substrate 3 having a plane orientation (100), the substrate 3 is mounted on the plate 4, disposed in a quartz glass furnace tube 2 in which a halogen lamp 1 is arranged outside, and annealed at 950 deg.C by the lamp 1 for 5 sec. Thus, as compared with a conventional method of annealing the substrate mounted on an Si substrate, temperature irregularity in the thicknesswise and planar directions of the substrate at the time of annealing can be alleviated to reduce the warpage of the substrate and the generation of a slip line.

Inventors

  • 👤 Michihisa Kono

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 01:51
CPC Classifications
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Claims Analysis

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References Cited (Backward Citations)

JPS6040694A Cited
JPS6273626A Cited

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