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JPS6468071A Expired / Lapsed JP ⏱️ 0.0 years remaining

Video signal clamping circuit

Assignee: Toshiba Corp
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Filing: 1987-09-08
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Granted: —
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Expires: 2007-09-08
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Abstract

Abstract PURPOSE:To stably and accurately clamp a video signal, by constituting the titled circuit so that a detected level error of a digital video signal is offset. CONSTITUTION:A video signal is clamped once by a clamping circuit 3 before converting it by an A/D converter 4, and after the A/D conversion, the level of the part (a part of a specific synchronizing chip or pedestal) to be attention of a digital video signal is compared with a desired clamping level, then thus obtained level error is subtracted from a digital video signal on order to offset level error, and a clamping action is achieved again. Since the DC level of an input video signal is thus aligned by clamping prior to the A/D conversion, the dynamic range of the A/D converter can be effectively utilized. Also, by re-clamping in the part of digital processing, influences of the variation among elements, secular change, or thermal variation are eliminated, hence a video signal can be stably and accurately clamped.

Inventors

  • 👤 Seiichi Tanaka
  • 👤 Yoshihisa Sakazaki

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 22:34
CPC Classifications
—

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